Simulation Results: aes/gcm_masked

 
09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.26 %
  • code
  • 98.15 %
  • assert
  • 98.57 %
  • func
  • 95.06 %
  • block
  • 98.23 %
  • line
  • 99.41 %
  • branch
  • 95.06 %
  • toggle
  • 98.13 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.56%
V2S
97.47%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 116.572us 1 1 100.00
smoke 50 50 100.00
aes_smoke 13.000s 779.040us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 2.000s 69.610us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 2.000s 79.004us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 7.000s 976.325us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 4.000s 111.870us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 3.000s 74.658us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 2.000s 79.004us 20 20 100.00
aes_csr_aliasing 4.000s 111.870us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 149 150 99.33
aes_smoke 13.000s 779.040us 50 50 100.00
aes_config_error 28.000s 1294.301us 49 50 98.00
aes_stress 20.000s 959.915us 50 50 100.00
key_length 149 150 99.33
aes_smoke 13.000s 779.040us 50 50 100.00
aes_config_error 28.000s 1294.301us 49 50 98.00
aes_stress 20.000s 959.915us 50 50 100.00
back2back 100 100 100.00
aes_stress 20.000s 959.915us 50 50 100.00
aes_b2b 34.000s 1250.893us 50 50 100.00
backpressure 50 50 100.00
aes_stress 20.000s 959.915us 50 50 100.00
multi_message 199 200 99.50
aes_smoke 13.000s 779.040us 50 50 100.00
aes_config_error 28.000s 1294.301us 49 50 98.00
aes_stress 20.000s 959.915us 50 50 100.00
aes_alert_reset 45.000s 3590.405us 50 50 100.00
failure_test 149 150 99.33
aes_man_cfg_err 4.000s 148.842us 50 50 100.00
aes_config_error 28.000s 1294.301us 49 50 98.00
aes_alert_reset 45.000s 3590.405us 50 50 100.00
trigger_clear_test 50 50 100.00
aes_clear 16.000s 678.691us 50 50 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 11.000s 196.917us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 10.000s 381.798us 1 1 100.00
reset_recovery 50 50 100.00
aes_alert_reset 45.000s 3590.405us 50 50 100.00
stress 50 50 100.00
aes_stress 20.000s 959.915us 50 50 100.00
sideload 99 100 99.00
aes_stress 20.000s 959.915us 50 50 100.00
aes_sideload 62.000s 2829.739us 49 50 98.00
deinitialization 50 50 100.00
aes_deinit 23.000s 1159.570us 50 50 100.00
stress_all 9 10 90.00
aes_stress_all 158.000s 10427.714us 9 10 90.00
gcm_save_and_restore 100 100 100.00
aes_gcm_save_restore 14.000s 673.575us 100 100 100.00
alert_test 50 50 100.00
aes_alert_test 6.000s 60.816us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 4.000s 89.393us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 4.000s 89.393us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 2.000s 69.610us 5 5 100.00
aes_csr_rw 2.000s 79.004us 20 20 100.00
aes_csr_aliasing 4.000s 111.870us 5 5 100.00
aes_same_csr_outstanding 4.000s 150.406us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 2.000s 69.610us 5 5 100.00
aes_csr_rw 2.000s 79.004us 20 20 100.00
aes_csr_aliasing 4.000s 111.870us 5 5 100.00
aes_same_csr_outstanding 4.000s 150.406us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 73.000s 3833.348us 50 50 100.00
fault_inject 670 700 95.71
aes_fi 56.000s 2427.516us 50 50 100.00
aes_control_fi 62.090s 0.000us 283 300 94.33
aes_cipher_fi 61.000s 0.000us 337 350 96.29
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 4.000s 529.936us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 4.000s 529.936us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 4.000s 529.936us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 4.000s 529.936us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 5.000s 541.121us 20 20 100.00
tl_intg_err 25 25 100.00
aes_sec_cm 6.000s 1843.085us 5 5 100.00
aes_tl_intg_err 8.000s 1697.297us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 8.000s 1697.297us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
aes_alert_reset 45.000s 3590.405us 50 50 100.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 4.000s 529.936us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 4.000s 529.936us 20 20 100.00
sec_cm_main_config_sparse 216 220 98.18
aes_smoke 13.000s 779.040us 50 50 100.00
aes_stress 20.000s 959.915us 50 50 100.00
aes_alert_reset 45.000s 3590.405us 50 50 100.00
aes_core_fi 914.000s 200000.000us 66 70 94.29
sec_cm_gcm_config_sparse 265 270 98.15
aes_gcm_save_restore 14.000s 673.575us 100 100 100.00
aes_config_error 28.000s 1294.301us 49 50 98.00
aes_stress 20.000s 959.915us 50 50 100.00
aes_core_fi 914.000s 200000.000us 66 70 94.29
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 4.000s 529.936us 20 20 100.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 4.000s 158.933us 50 50 100.00
aes_stress 20.000s 959.915us 50 50 100.00
sec_cm_key_sideload 99 100 99.00
aes_stress 20.000s 959.915us 50 50 100.00
aes_sideload 62.000s 2829.739us 49 50 98.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 4.000s 158.933us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 4.000s 158.933us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 4.000s 158.933us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 4.000s 158.933us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 4.000s 158.933us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 20.000s 959.915us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 20.000s 959.915us 50 50 100.00
sec_cm_main_fsm_sparse 50 50 100.00
aes_fi 56.000s 2427.516us 50 50 100.00
sec_cm_main_fsm_redun 720 750 96.00
aes_fi 56.000s 2427.516us 50 50 100.00
aes_control_fi 62.090s 0.000us 283 300 94.33
aes_cipher_fi 61.000s 0.000us 337 350 96.29
aes_ctr_fi 5.000s 50.252us 50 50 100.00
sec_cm_cipher_fsm_sparse 50 50 100.00
aes_fi 56.000s 2427.516us 50 50 100.00
sec_cm_cipher_fsm_redun 670 700 95.71
aes_fi 56.000s 2427.516us 50 50 100.00
aes_control_fi 62.090s 0.000us 283 300 94.33
aes_cipher_fi 61.000s 0.000us 337 350 96.29
sec_cm_cipher_ctr_redun 337 350 96.29
aes_cipher_fi 61.000s 0.000us 337 350 96.29
sec_cm_ctr_fsm_sparse 50 50 100.00
aes_fi 56.000s 2427.516us 50 50 100.00
sec_cm_ctr_fsm_redun 383 400 95.75
aes_fi 56.000s 2427.516us 50 50 100.00
aes_control_fi 62.090s 0.000us 283 300 94.33
aes_ctr_fi 5.000s 50.252us 50 50 100.00
sec_cm_ghash_fsm_sparse 50 50 100.00
aes_fi 56.000s 2427.516us 50 50 100.00
sec_cm_ctrl_sparse 720 750 96.00
aes_fi 56.000s 2427.516us 50 50 100.00
aes_control_fi 62.090s 0.000us 283 300 94.33
aes_cipher_fi 61.000s 0.000us 337 350 96.29
aes_ctr_fi 5.000s 50.252us 50 50 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
aes_alert_reset 45.000s 3590.405us 50 50 100.00
sec_cm_main_fsm_local_esc 720 750 96.00
aes_fi 56.000s 2427.516us 50 50 100.00
aes_control_fi 62.090s 0.000us 283 300 94.33
aes_cipher_fi 61.000s 0.000us 337 350 96.29
aes_ctr_fi 5.000s 50.252us 50 50 100.00
sec_cm_cipher_fsm_local_esc 720 750 96.00
aes_fi 56.000s 2427.516us 50 50 100.00
aes_control_fi 62.090s 0.000us 283 300 94.33
aes_cipher_fi 61.000s 0.000us 337 350 96.29
aes_ctr_fi 5.000s 50.252us 50 50 100.00
sec_cm_ctr_fsm_local_esc 383 400 95.75
aes_fi 56.000s 2427.516us 50 50 100.00
aes_control_fi 62.090s 0.000us 283 300 94.33
aes_ctr_fi 5.000s 50.252us 50 50 100.00
sec_cm_ghash_fsm_local_esc 140 140 100.00
aes_ghash_fi 9.000s 408.485us 90 90 100.00
aes_fi 56.000s 2427.516us 50 50 100.00
sec_cm_data_reg_local_esc 670 700 95.71
aes_fi 56.000s 2427.516us 50 50 100.00
aes_control_fi 62.090s 0.000us 283 300 94.33
aes_cipher_fi 61.000s 0.000us 337 350 96.29
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 63.000s 4334.341us 0 10 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 10 test runs
aes_control_fi 29561021373748047956969942785393449378411307474824067658066816509861895143037 None
aes_cipher_fi 59393344499191350046334938263778764844600475279241837993843495454883446158723 None
aes_control_fi 59754304608117779235157433323205374145281730744710227520906275341073666824355 None
aes_control_fi 36322136444697506704521995231626749285900718418338831791883132054713796121079 None
aes_control_fi 71240052086742974849535082283911413308671900696891531368675679244076615978502 None
aes_cipher_fi 38002603036453596172781648832097410071973724351006762564693389645300457618230 None
aes_control_fi 73164572340595298734928720081607078036972772026406387559378711923606162878141 None
aes_control_fi 43763492009027133585411251478373934347153939408481218670686094885519041642308 None
aes_control_fi 19042556247824153475776370881336975317038605641656367757308304989820177747999 None
aes_cipher_fi 65789673555463460962232899018699917404701300962902602602739823301282910507081 None
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 10 test runs
aes_control_fi 88782310619445052788607825588356661663132960563841003928239962446634700247229 142
UVM_INFO @ 10020741302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 88887382851699835205085820903179485626589981039302618322567653829247624303762 154
UVM_INFO @ 10027552742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 29324445604645294343257623856271143039734260252276343657443193757954538913055 151
UVM_INFO @ 10028460533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 15714503705630972254508608815629430230315649863529516949403827062743989754780 147
UVM_INFO @ 10007451964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 87202022437930792293612690893238204098508008578578972878288787965859450914437 147
UVM_INFO @ 10018593064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 53557005086269786499272467330927273313451004858587861503803977618745823207955 149
UVM_INFO @ 10188748266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 99001620738442986129845040932160186595585653690180006459485650270320166786759 142
UVM_INFO @ 10016151463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 86703623283767033445635726199013897541520817663115533689311255018917269305835 148
UVM_INFO @ 10015337634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 90744092294657190230904696797233631087789887171061997768139681053310150731028 163
UVM_INFO @ 10009258112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 63307435445231531565993126677711324624609311919082268878407705384626100417131 147
UVM_INFO @ 10009696120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 8 test runs
aes_cipher_fi 30255562808054899420576275954158936505272972340786951539084284465835988995765 146
UVM_INFO @ 10063376769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 55247254033099417678995156736086238706658372267593877369703514635724891005985 147
UVM_INFO @ 10008290838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 40417103741108768593090344409971551397010054920826202792650633400640671699464 146
UVM_INFO @ 10011565997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 23174854961960117603207949529443647118212012432569035396486920443289023400099 143
UVM_INFO @ 10005720059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 8718219926738540224671327431372163931126028818627884436059431391718427513937 149
UVM_INFO @ 10013938166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 98716790890262182903452377368785036916954549271381234125346913839863919726930 159
UVM_INFO @ 10013039358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 96760344946134268932813427820490033109636077399477377555097458880626449316253 149
UVM_INFO @ 10026777326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 54577798936649880350578735709950831775684939646956615414812030127214471939154 143
UVM_INFO @ 10012427846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 3 test runs
aes_stress_all_with_rand_reset 64949643355036744901721342824034940094594493363866837573046477158302719484070 2031
UVM_INFO @ 4334340879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 47001835371856982284921748262039842720516057082868471559177691549717420164077 967
UVM_INFO @ 803106328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 90885801291568436172563376792817696040209063789327187842133755397401855905796 1732
UVM_INFO @ 1949463041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 3 test runs
aes_core_fi 41717391311221116284881419781079533339366588048386783104048506745750336196084 143
UVM_INFO @ 10032249341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 37055411470546127161504951909044249253674123762281970751382134689380091380286 155
UVM_INFO @ 10018897758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 33680250520987368643731445410667813743715706360160793641385607842423253775259 157
UVM_INFO @ 10112791138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
aes_stress_all_with_rand_reset 22039100896643886884598325852923531384050267178950473765616148071887324412197 184
UVM_INFO @ 400326728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 5657824429335077221559365319904357122169531119624664720529818258993749609559 291
UVM_INFO @ 1487713888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 2 test runs
aes_stress_all_with_rand_reset 17304323575963410721782616707771423685499209213463230312499912480013807783710 323
UVM_INFO @ 1030924570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 26894375474745242491807472089953378584275590198824507797328546883095541900976 388
UVM_INFO @ 5715315538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 2 test runs
aes_stress_all_with_rand_reset 73754263710609568954910095199753047248435274129542183758677133734020240342937 335
UVM_INFO @ 897438106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 60374881498913754091728164897842834152202376024099755090614573354658370120818 764
UVM_INFO @ 2320372742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '*' in file '/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_*/aes_scoreboard.sv' at time * PS + *. 2 test runs
aes_config_error 96954590918822432060335774227623682424730716661415373942521047982355660827710 1687
xmsim: *E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '748' in file '/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 128249554 PS + 10.
xmsim: *E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '748' in file '/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 128249554 PS + 10.
xmsim: *E,MEMALC: Memory not allocated for actual argument 'predicted_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '748' in file '/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 128249554 PS + 10.
xmsim: *E,MEMALC: Memory not allocated for actual argument 'predicted_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '748' in file '/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 128249554 PS + 10.
aes_sideload 100536354681900086265036654637281844738022298570675712800999918246105427068221 8831
xmsim: *E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '748' in file '/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 151017008 PS + 10.
xmsim: *E,MEMALC: Memory not allocated for actual argument 'input_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '748' in file '/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 151017008 PS + 10.
xmsim: *E,MEMALC: Memory not allocated for actual argument 'predicted_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '748' in file '/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 151017008 PS + 10.
xmsim: *E,MEMALC: Memory not allocated for actual argument 'predicted_msg', passed to DPI task/function 'c_dpi_aes_crypt_message' call at line '748' in file '/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_aes_env_0.1/aes_scoreboard.sv' at time 151017008 PS + 10.
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=45) 1 test run
aes_stress_all 60659829814986388546177602008677353849281344259325545021697443870922530463729 992804
UVM_INFO @ 10427714151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 98531623587703092196924665647817118876746169353858460527370900740810648550809 619
UVM_INFO @ 3861731464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
aes_core_fi 46605431484735602498620877264020260356265227750606353510251912617332030579589 162
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) 1 test run
aes_cipher_fi 36852067008957491793856897593882661734344696118329358617903256830525550871277 139
UVM_INFO @ 10018043013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) 1 test run
aes_cipher_fi 56832618159851417367422805285610963644503255638795083901727969031619163313497 139
UVM_INFO @ 10008223472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---