Simulation Results: aes/gcm_unmasked

 
09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.91 %
  • code
  • 94.31 %
  • assert
  • 98.13 %
  • func
  • 86.29 %
  • block
  • 95.10 %
  • line
  • 96.46 %
  • branch
  • 89.89 %
  • toggle
  • 97.99 %
  • FSM
  • 92.91 %
Validation stages
V1
100.00%
V2
99.14%
V2S
96.52%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 67.931us 1 1 100.00
smoke 50 50 100.00
aes_smoke 3.000s 64.839us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 3.000s 69.851us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 3.000s 119.665us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 5.000s 145.199us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 3.000s 157.147us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 118.327us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 3.000s 119.665us 20 20 100.00
aes_csr_aliasing 3.000s 157.147us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 3.000s 64.839us 50 50 100.00
aes_config_error 6.000s 462.008us 50 50 100.00
aes_stress 3.000s 118.185us 50 50 100.00
key_length 150 150 100.00
aes_smoke 3.000s 64.839us 50 50 100.00
aes_config_error 6.000s 462.008us 50 50 100.00
aes_stress 3.000s 118.185us 50 50 100.00
back2back 100 100 100.00
aes_stress 3.000s 118.185us 50 50 100.00
aes_b2b 8.000s 175.040us 50 50 100.00
backpressure 50 50 100.00
aes_stress 3.000s 118.185us 50 50 100.00
multi_message 199 200 99.50
aes_smoke 3.000s 64.839us 50 50 100.00
aes_config_error 6.000s 462.008us 50 50 100.00
aes_stress 3.000s 118.185us 50 50 100.00
aes_alert_reset 5.000s 155.419us 49 50 98.00
failure_test 149 150 99.33
aes_man_cfg_err 3.000s 74.469us 50 50 100.00
aes_config_error 6.000s 462.008us 50 50 100.00
aes_alert_reset 5.000s 155.419us 49 50 98.00
trigger_clear_test 48 50 96.00
aes_clear 4.000s 294.391us 48 50 96.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 537.001us 1 1 100.00
reset_recovery 49 50 98.00
aes_alert_reset 5.000s 155.419us 49 50 98.00
stress 50 50 100.00
aes_stress 3.000s 118.185us 50 50 100.00
sideload 100 100 100.00
aes_stress 3.000s 118.185us 50 50 100.00
aes_sideload 3.000s 239.528us 50 50 100.00
deinitialization 49 50 98.00
aes_deinit 891.000s 200000.000us 49 50 98.00
stress_all 9 10 90.00
aes_stress_all 30.000s 583.956us 9 10 90.00
alert_test 50 50 100.00
aes_alert_test 3.000s 66.837us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 3.000s 195.261us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 3.000s 195.261us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 3.000s 69.851us 5 5 100.00
aes_csr_rw 3.000s 119.665us 20 20 100.00
aes_csr_aliasing 3.000s 157.147us 5 5 100.00
aes_same_csr_outstanding 3.000s 82.520us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 3.000s 69.851us 5 5 100.00
aes_csr_rw 3.000s 119.665us 20 20 100.00
aes_csr_aliasing 3.000s 157.147us 5 5 100.00
aes_same_csr_outstanding 3.000s 82.520us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 5.000s 153.565us 50 50 100.00
fault_inject 664 700 94.86
aes_fi 3287.000s 200000.000us 49 50 98.00
aes_control_fi 61.000s 0.000us 286 300 95.33
aes_cipher_fi 62.072s 0.000us 329 350 94.00
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 3.000s 264.633us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 3.000s 264.633us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 3.000s 264.633us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 3.000s 264.633us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 164.635us 20 20 100.00
tl_intg_err 25 25 100.00
aes_sec_cm 5.000s 817.998us 5 5 100.00
aes_tl_intg_err 3.000s 113.224us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 3.000s 113.224us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 49 50 98.00
aes_alert_reset 5.000s 155.419us 49 50 98.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 264.633us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 264.633us 20 20 100.00
sec_cm_main_config_sparse 213 220 96.82
aes_smoke 3.000s 64.839us 50 50 100.00
aes_stress 3.000s 118.185us 50 50 100.00
aes_alert_reset 5.000s 155.419us 49 50 98.00
aes_core_fi 293.000s 10009.642us 64 70 91.43
sec_cm_gcm_config_sparse 164 170 96.47
aes_config_error 6.000s 462.008us 50 50 100.00
aes_stress 3.000s 118.185us 50 50 100.00
aes_core_fi 293.000s 10009.642us 64 70 91.43
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 264.633us 20 20 100.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 3.000s 105.646us 50 50 100.00
aes_stress 3.000s 118.185us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 3.000s 118.185us 50 50 100.00
aes_sideload 3.000s 239.528us 50 50 100.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 3.000s 105.646us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 3.000s 105.646us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 3.000s 105.646us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 3.000s 105.646us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 3.000s 105.646us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 3.000s 118.185us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 3.000s 118.185us 50 50 100.00
sec_cm_main_fsm_sparse 49 50 98.00
aes_fi 3287.000s 200000.000us 49 50 98.00
sec_cm_main_fsm_redun 714 750 95.20
aes_fi 3287.000s 200000.000us 49 50 98.00
aes_control_fi 61.000s 0.000us 286 300 95.33
aes_cipher_fi 62.072s 0.000us 329 350 94.00
aes_ctr_fi 3.000s 79.238us 50 50 100.00
sec_cm_cipher_fsm_sparse 49 50 98.00
aes_fi 3287.000s 200000.000us 49 50 98.00
sec_cm_cipher_fsm_redun 664 700 94.86
aes_fi 3287.000s 200000.000us 49 50 98.00
aes_control_fi 61.000s 0.000us 286 300 95.33
aes_cipher_fi 62.072s 0.000us 329 350 94.00
sec_cm_cipher_ctr_redun 329 350 94.00
aes_cipher_fi 62.072s 0.000us 329 350 94.00
sec_cm_ctr_fsm_sparse 49 50 98.00
aes_fi 3287.000s 200000.000us 49 50 98.00
sec_cm_ctr_fsm_redun 385 400 96.25
aes_fi 3287.000s 200000.000us 49 50 98.00
aes_control_fi 61.000s 0.000us 286 300 95.33
aes_ctr_fi 3.000s 79.238us 50 50 100.00
sec_cm_ghash_fsm_sparse 49 50 98.00
aes_fi 3287.000s 200000.000us 49 50 98.00
sec_cm_ctrl_sparse 714 750 95.20
aes_fi 3287.000s 200000.000us 49 50 98.00
aes_control_fi 61.000s 0.000us 286 300 95.33
aes_cipher_fi 62.072s 0.000us 329 350 94.00
aes_ctr_fi 3.000s 79.238us 50 50 100.00
sec_cm_main_fsm_global_esc 49 50 98.00
aes_alert_reset 5.000s 155.419us 49 50 98.00
sec_cm_main_fsm_local_esc 714 750 95.20
aes_fi 3287.000s 200000.000us 49 50 98.00
aes_control_fi 61.000s 0.000us 286 300 95.33
aes_cipher_fi 62.072s 0.000us 329 350 94.00
aes_ctr_fi 3.000s 79.238us 50 50 100.00
sec_cm_cipher_fsm_local_esc 714 750 95.20
aes_fi 3287.000s 200000.000us 49 50 98.00
aes_control_fi 61.000s 0.000us 286 300 95.33
aes_cipher_fi 62.072s 0.000us 329 350 94.00
aes_ctr_fi 3.000s 79.238us 50 50 100.00
sec_cm_ctr_fsm_local_esc 385 400 96.25
aes_fi 3287.000s 200000.000us 49 50 98.00
aes_control_fi 61.000s 0.000us 286 300 95.33
aes_ctr_fi 3.000s 79.238us 50 50 100.00
sec_cm_ghash_fsm_local_esc 49 50 98.00
aes_fi 3287.000s 200000.000us 49 50 98.00
sec_cm_data_reg_local_esc 664 700 94.86
aes_fi 3287.000s 200000.000us 49 50 98.00
aes_control_fi 61.000s 0.000us 286 300 95.33
aes_cipher_fi 62.072s 0.000us 329 350 94.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 33.000s 7625.646us 0 10 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 14 test runs
aes_control_fi 61772789345563304071292439111305711906179671597682032741938208134726883000048 None
aes_cipher_fi 14035877690815324518298934573732956176159508688439102701475603309009640486429 None
aes_cipher_fi 49964176165155848612114341723913169420286923219708115888480308134676895865015 None
aes_control_fi 104610774576734934232936802494398852937525608690303111392920438958581278251667 None
aes_control_fi 40643582546000263407326596062305104639780369230499033600549167244595780635068 None
aes_cipher_fi 64023498103345212899816880013675858750016390601514921133991963190414543559149 None
aes_cipher_fi 41616010431138896242184406002092727724497251070909438820378954142917589066092 None
aes_cipher_fi 20695743070258165954315349410248205135309867373869685215486459712559210658140 None
aes_cipher_fi 4078200294122553461379163040931776124102584017618594201377683791305959458647 None
aes_cipher_fi 56491576423262431878188434933042987508607630008080806555465233831339992589410 None
aes_cipher_fi 45563101659481291571376473120468153306435825438663417640998691543620389174656 None
aes_cipher_fi 45679511142986436504884747193040476197175388778949455238555457326417749998728 None
aes_cipher_fi 101501989731738294743695708768129883359333917092195483093598526352586006033213 None
aes_cipher_fi 17059445470356541323576561997666684185327683334053693636971850375674855948881 None
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 10 test runs
aes_control_fi 12892121509459158623475980239094224505923910072288790271124625395904832165515 139
UVM_INFO @ 10006520756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 105242509407666181391457394851950619241408347558642272490561341253766429303141 154
UVM_INFO @ 10009152326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 83096960877494134049403818547283294010730400710849206236604916906835185108064 146
UVM_INFO @ 10010999508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 79392364902522389099043540252168690577071458006080325095353587056204829898643 143
UVM_INFO @ 10013945898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 86995139416980809278733936609760013580447214534368166047502499861665841885840 155
UVM_INFO @ 10008498278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 13391972478837090326170300461423203730450659646222757819752359942927778756901 148
UVM_INFO @ 10003411594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 114136326830146582271026911098808413055403744004150508500651866556533482608126 140
UVM_INFO @ 10004828397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 33865715554634503696582510260760219835784159381635937152170456790730392024327 152
UVM_INFO @ 10011664886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 12967207957965418746937845128967451825979492601505889515522404210605553703632 151
UVM_INFO @ 10006022106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 12983226136224081709366033192709971364432910549701278522703195629562576554030 155
UVM_INFO @ 10009844326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 10 test runs
aes_cipher_fi 47663495686484753619146076136882574093344451489195674563211922448136643855145 156
UVM_INFO @ 10010031488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 86528555105554284859990040331168949347532644750410424989123393312212522661538 144
UVM_INFO @ 10016938348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 108735514457668963948279077622753954453524744584765102155731395691676443845395 147
UVM_INFO @ 10003355221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 7717126822943785152403439362273880778037110760164650477379336323574940625677 155
UVM_INFO @ 10005508859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 40229462593387304150553641628263974878042142945591593360559272606020580167827 144
UVM_INFO @ 10005855354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 107522703050250112049928067047465113451703022540751062661084969707733678157455 144
UVM_INFO @ 10005657978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 107981738275644727170400119223523071930442137242052113089586605778241898980016 154
UVM_INFO @ 10010000910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 33214800075008972269794375291526317133403249148040865261603965222561478199826 142
UVM_INFO @ 10008226655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 15033554990204221918991654908005836716047198714470331909016845154161394465028 155
UVM_INFO @ 10004865156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 15478620585382603059034943097145896777906837171246298305266786901569343958170 147
UVM_INFO @ 10009472369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 3 test runs
aes_stress_all_with_rand_reset 113015611673365146687709855528378196966795016577139158365104907553574526774090 2411
UVM_INFO @ 7625645868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 81607470072449025905735970244105443470141675538918215568168141965322209599076 1423
UVM_INFO @ 771183119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 94726882396023281683504330643040302686157834720180762711920763793968988726701 826
UVM_INFO @ 569593066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 3 test runs
aes_deinit 16684900346843487727378626825001747101977935716247207282968632901149715784001 175
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_fi 15205050089453732664928606193978292514790414212799449274755370396631811592302 22553808
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 61368770103109018090917840086996620494559175558971578254225824909921586960567 151
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:93) [aes_core_fi_vseq] wait timeout occurred! 3 test runs
aes_core_fi 114619322965841527594956289775120965298286115669988993215133066788731438425224 147
UVM_INFO @ 10080185785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 61343944436316269124326135335506873849872228672368175160852400711568990367107 152
UVM_INFO @ 10044843489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 87026124129918261337241648751088548023292440889254743404455522115359319870456 145
UVM_INFO @ 10033436475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
aes_stress_all_with_rand_reset 74204835942788472352987868441183310464259872060525997285189532413863053589791 171
UVM_INFO @ 1197520468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 9919343671336745921608431417174975604777728659025163721510556863423628559187 644
UVM_INFO @ 1565095217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:785) scoreboard [scoreboard] # * 2 test runs
aes_clear 30409799110665199288712181976643534856406914991888674535444414863010117662814 1092
TEST FAILED MESSAGES DID NOT MATCH
0 f0 e8 83 0
1 c7 34 7a 0
aes_clear 83251146232631590125888431314492112103775871702475657182624045366345820949715 3306
TEST FAILED MESSAGES DID NOT MATCH
0 7a 6a a3 0
1 25 fb 75 0
UVM_FATAL (aes_base_vseq.sv:76) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 2 test runs
aes_stress_all_with_rand_reset 68694095669275078453522485053184175829188059097771223228531745535077507158248 739
UVM_INFO @ 208388775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 15261032043501822813079159629963051024185348892061156699536592753283731828609 174
UVM_INFO @ 17465235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1112): Assertion AesModeValid has failed 2 test runs
aes_stress_all_with_rand_reset 15710874079082818755792387455971970180737224380634887224388394584813171877033 928
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 697254985 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 697254985 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 697254985 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
UVM_ERROR @ 697254985 ps: (aes_core.sv:1112) [ASSERT FAILED] AesModeValid
aes_alert_reset 40532631953514810957930220841113858639359286401148331644277648502307500140430 1400
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 49689975 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 49689975 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 49689975 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
UVM_ERROR @ 49689975 ps: (aes_core.sv:1112) [ASSERT FAILED] AesModeValid
UVM_FATAL (aes_base_vseq.sv:76) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 100043466890566922486828131398714121812106242357811042917425169907001487953392 639
UVM_INFO @ 535249834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 90241236869029342283753384423022401736780142779067863283080235871702386712660 340
UVM_INFO @ 497604343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) 1 test run
aes_stress_all 69599512257535630376875310128682456927144295218346062565678550397497080757331 14725
UVM_INFO @ 4665860454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 1 test run
aes_core_fi 9656857930727759547307176845581717257946920410302542739396639187158153849521 147
UVM_INFO @ 10011570937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) 1 test run
aes_core_fi 14722161538608499535100775055191630012013304782908604425310214150502281270276 146
UVM_INFO @ 10010421677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) 1 test run
aes_core_fi 77246160024519512884651918676542510846178110745102174097956864357513146432817 141
UVM_INFO @ 10009641763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---