Simulation Results: aon_timer

 
09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.47 %
  • code
  • 95.75 %
  • assert
  • 96.67 %
  • func
  • 100.00 %
  • block
  • 99.32 %
  • line
  • 99.34 %
  • branch
  • 99.00 %
  • toggle
  • 88.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
aon_timer_smoke 3.000s 678.798us 5 5 100.00
csr_hw_reset 5 5 100.00
aon_timer_csr_hw_reset 25.000s 734.969us 5 5 100.00
csr_rw 20 20 100.00
aon_timer_csr_rw 3.000s 506.752us 20 20 100.00
csr_bit_bash 5 5 100.00
aon_timer_csr_bit_bash 35.000s 7967.828us 5 5 100.00
csr_aliasing 5 5 100.00
aon_timer_csr_aliasing 28.000s 471.076us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aon_timer_csr_mem_rw_with_rand_reset 21.000s 521.109us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aon_timer_csr_rw 3.000s 506.752us 20 20 100.00
aon_timer_csr_aliasing 28.000s 471.076us 5 5 100.00
mem_walk 5 5 100.00
aon_timer_mem_walk 2.000s 295.605us 5 5 100.00
mem_partial_access 5 5 100.00
aon_timer_mem_partial_access 2.000s 378.320us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
prescaler 15 15 100.00
aon_timer_prescaler 38.000s 29189.778us 15 15 100.00
jump 5 5 100.00
aon_timer_jump 3.000s 640.857us 5 5 100.00
stress_all 15 15 100.00
aon_timer_stress_all 323.000s 178396.827us 15 15 100.00
alert_test 50 50 100.00
aon_timer_alert_test 27.000s 277.477us 50 50 100.00
intr_test 50 50 100.00
aon_timer_intr_test 3.000s 436.411us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aon_timer_tl_errors 4.000s 445.504us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aon_timer_tl_errors 4.000s 445.504us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aon_timer_csr_hw_reset 25.000s 734.969us 5 5 100.00
aon_timer_csr_rw 3.000s 506.752us 20 20 100.00
aon_timer_csr_aliasing 28.000s 471.076us 5 5 100.00
aon_timer_same_csr_outstanding 11.000s 2800.362us 20 20 100.00
tl_d_partial_access 50 50 100.00
aon_timer_csr_hw_reset 25.000s 734.969us 5 5 100.00
aon_timer_csr_rw 3.000s 506.752us 20 20 100.00
aon_timer_csr_aliasing 28.000s 471.076us 5 5 100.00
aon_timer_same_csr_outstanding 11.000s 2800.362us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 23 25 92.00
aon_timer_sec_cm 11.000s 7985.699us 4 5 80.00
aon_timer_tl_intg_err 19.000s 8155.116us 19 20 95.00
sec_cm_bus_integrity 19 20 95.00
aon_timer_tl_intg_err 19.000s 8155.116us 19 20 95.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_threshold 5 5 100.00
aon_timer_smoke_max_thold 4.000s 702.148us 5 5 100.00
min_threshold 5 5 100.00
aon_timer_smoke_min_thold 4.000s 675.123us 5 5 100.00
wkup_count_hi_cdc 5 5 100.00
aon_timer_wkup_count_cdc_hi 11.000s 3192.962us 5 5 100.00
custom_intr 10 10 100.00
aon_timer_custom_intr 4.000s 726.059us 10 10 100.00
alternating_on_off 5 5 100.00
aon_timer_alternating_enable_on_off 44.000s 4008.932us 5 5 100.00
stress_all_with_rand_reset 15 15 100.00
aon_timer_stress_all_with_rand_reset 37.000s 22696.875us 15 15 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1028) virtual_sequencer [aon_timer_common_vseq] expect alert:fatal_fault to fire 2 test runs
aon_timer_sec_cm 67858489493534750314581762439989053893415031367311152637550711501896032269670 86
UVM_INFO @ 496913107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aon_timer_tl_intg_err 110297621162002260614661427135611551166944490743985874130331669443606211400355 91
UVM_INFO @ 336810024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---