Simulation Results

Simulation Results: csrng

09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.36 %

code
96.26 %

assert
95.85 %

func
90.97 %

block
98.62 %

line
99.61 %

branch
96.55 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		96.80%
V2S		99.70%
V3		0.00%

105/105 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	csrng_smoke	33.000s	82.382us	50	50	100.00
csr_hw_reset				5	5	100.00
	csrng_csr_hw_reset	31.000s	18.734us	5	5	100.00
csr_rw				20	20	100.00
	csrng_csr_rw	32.000s	59.316us	20	20	100.00
csr_bit_bash				5	5	100.00
	csrng_csr_bit_bash	34.000s	114.423us	5	5	100.00
csr_aliasing				5	5	100.00
	csrng_csr_aliasing	35.000s	259.016us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	csrng_csr_mem_rw_with_rand_reset	32.000s	49.689us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	csrng_csr_rw	32.000s	59.316us	20	20	100.00
	csrng_csr_aliasing	35.000s	259.016us	5	5	100.00

1423/1470 passed

96.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	33.000s	77.994us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	46.000s	426.088us	500	500	100.00
err				500	500	100.00
	csrng_err	32.000s	20.876us	500	500	100.00
cmds				7	50	14.00
	csrng_cmds	157.000s	10595.228us	7	50	14.00
life cycle				7	50	14.00
	csrng_cmds	157.000s	10595.228us	7	50	14.00
stress_all				46	50	92.00
	csrng_stress_all	1949.000s	194095.367us	46	50	92.00
intr_test				50	50	100.00
	csrng_intr_test	31.000s	14.674us	50	50	100.00
alert_test				50	50	100.00
	csrng_alert_test	32.000s	35.465us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	csrng_tl_errors	31.000s	168.810us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	csrng_tl_errors	31.000s	168.810us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	csrng_csr_hw_reset	31.000s	18.734us	5	5	100.00
	csrng_csr_rw	32.000s	59.316us	20	20	100.00
	csrng_csr_aliasing	35.000s	259.016us	5	5	100.00
	csrng_same_csr_outstanding	34.000s	148.489us	20	20	100.00
tl_d_partial_access				50	50	100.00
	csrng_csr_hw_reset	31.000s	18.734us	5	5	100.00
	csrng_csr_rw	32.000s	59.316us	20	20	100.00
	csrng_csr_aliasing	35.000s	259.016us	5	5	100.00
	csrng_same_csr_outstanding	34.000s	148.489us	20	20	100.00

V2S

1341/1345 passed

99.70 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	csrng_sec_cm	32.000s	48.471us	5	5	100.00
	csrng_tl_intg_err	28.000s	225.627us	20	20	100.00
sec_cm_config_regwen				70	70	100.00
	csrng_regwen	32.000s	15.356us	50	50	100.00
	csrng_csr_rw	32.000s	59.316us	20	20	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	46.000s	426.088us	500	500	100.00
sec_cm_intersig_mubi				46	50	92.00
	csrng_stress_all	1949.000s	194095.367us	46	50	92.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	33.000s	77.994us	200	200	100.00
	csrng_err	32.000s	20.876us	500	500	100.00
	csrng_sec_cm	32.000s	48.471us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	33.000s	77.994us	200	200	100.00
	csrng_err	32.000s	20.876us	500	500	100.00
	csrng_sec_cm	32.000s	48.471us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	33.000s	77.994us	200	200	100.00
	csrng_err	32.000s	20.876us	500	500	100.00
	csrng_sec_cm	32.000s	48.471us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	33.000s	77.994us	200	200	100.00
	csrng_err	32.000s	20.876us	500	500	100.00
	csrng_sec_cm	32.000s	48.471us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	33.000s	77.994us	200	200	100.00
	csrng_err	32.000s	20.876us	500	500	100.00
	csrng_sec_cm	32.000s	48.471us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	46.000s	426.088us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	33.000s	77.994us	200	200	100.00
	csrng_err	32.000s	20.876us	500	500	100.00
sec_cm_constants_lc_gated				46	50	92.00
	csrng_stress_all	1949.000s	194095.367us	46	50	92.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	46.000s	426.088us	500	500	100.00
sec_cm_tile_link_bus_integrity				20	20	100.00
	csrng_tl_intg_err	28.000s	225.627us	20	20	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	33.000s	77.994us	200	200	100.00
	csrng_err	32.000s	20.876us	500	500	100.00
	csrng_sec_cm	32.000s	48.471us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	33.000s	77.994us	200	200	100.00
	csrng_err	32.000s	20.876us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	33.000s	77.994us	200	200	100.00
	csrng_err	32.000s	20.876us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	33.000s	77.994us	200	200	100.00
	csrng_err	32.000s	20.876us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	33.000s	77.994us	200	200	100.00
	csrng_err	32.000s	20.876us	500	500	100.00
	csrng_sec_cm	32.000s	48.471us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	33.000s	77.994us	200	200	100.00
	csrng_err	32.000s	20.876us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	10801.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])				39 test runs
	csrng_cmds	44763166332267961684281887110325895724253489966504174047204266318679351725024	130	UVM_INFO @ 39140819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	78889666293881094667862607723921911703194184217219322613716704002832200889968	140	UVM_INFO @ 164653233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	113719698179992553258883194483484690232737706689500158844209981620634383383545	130	UVM_INFO @ 321707479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	54050097090697769056076924499546587470819041523196474662846412472131144815882	140	UVM_INFO @ 705495931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	43432100882221033638650251861954393330425134716848902068280811519981491175046	130	UVM_INFO @ 75742340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	114073216166293664359402528985834913755503895334926460421194687083982596269774	130	UVM_INFO @ 62444978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	24956725063637040294359402449457251479725201510625340026927046287253974192891	130	UVM_INFO @ 127275320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	91563616364834900953279179440494258502203599189313313255222093186184481099375	130	UVM_INFO @ 56853964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	109999763590698658414347932953634583381282539828458513452511238517491180118313	140	UVM_INFO @ 201406402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	55058133863484068146738274159960923550733306429737736339365890198683225264037	140	UVM_INFO @ 178691406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	83980957728870193328658281524498961905589915487877379666200088024724384665573	130	UVM_INFO @ 8978198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	49698167460012108438733779037894962300663535567837503243045900852997307702198	130	UVM_INFO @ 74985585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	7985385843265499447381849474213146801494732144991407049081632583215010393546	130	UVM_INFO @ 157555969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	109789660443372638841838921484527525703975395735970777875668639567956616789666	140	UVM_INFO @ 519314925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	107716167617206592690902461786951252488243075845465230551022210208583890787772	130	UVM_INFO @ 43269253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	46790989796843771968767994824571617830374209565567153183366771000560124543588	130	UVM_INFO @ 407028279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	10729301258485350061727050864914866656786910400393858089401320441902132336646	130	UVM_INFO @ 459169135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	97236564698890031449606919232753603191580511055795360194290854020944449230936	130	UVM_INFO @ 44602151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	10272540658377865417487658290390839221390825747563256366623560140736333906588	130	UVM_INFO @ 109481830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	114967256856103530603063244673421500194943083569200946475624335340581867284859	130	UVM_INFO @ 57287545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	65701204134696530288000255137913256296819041771251116471101943268020231033011	130	UVM_INFO @ 364563691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	83427364091595313945266548526412418415869464342611349930797311839632881870600	130	UVM_INFO @ 42472764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	111422303791169163187964933646749390240659916363140318954078516078418924174225	130	UVM_INFO @ 82834203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	31623826871608174372327068122519064549536004407744654302809348048259513268200	130	UVM_INFO @ 206876000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	104781835164673511097311030177551358633009432530316825109676540638057400268537	140	UVM_INFO @ 2236469546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	19739153495407750582658305391838869873313469979583449046202343799580934793865	130	UVM_INFO @ 100384897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	35874133181194157215927602605620591563620133105231418331975324871458335644146	130	UVM_INFO @ 49362281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	51621248216379491929936773282956219162336199064373214769351527628495894072925	130	UVM_INFO @ 153388785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	9431622970824215609871456945096518671201164955300015685996003478140791858208	130	UVM_INFO @ 77801615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	109430547192084217607597402537355130631413579506395276294024823553027099396697	130	UVM_INFO @ 129813257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	72403574363048620854190104949865138900311903214115590629795851102819296289595	130	UVM_INFO @ 65495000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	10650921601511477596821362299507064134305732081500349971415015675407530688467	130	UVM_INFO @ 130179304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	37491376898154217456734730552775250899848501922571884782677623104626656903004	130	UVM_INFO @ 205887035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	31939527287181011349542618881177440639404819217724839705985183828490809938701	130	UVM_INFO @ 131408604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	42438256230988923287952405668697099226591232706773617960068360308200430581343	130	UVM_INFO @ 75027789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	88865481129937776885187448471911149563392448294264823272715608934617183113672	130	UVM_INFO @ 109702094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	78384894029515946361178385335203997055800466409727843183727439542466845386514	130	UVM_INFO @ 42058264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	1896261932630682904645154419090845470912833829252816326697588506033501523341	130	UVM_INFO @ 58026277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	52980894018485740711344221423443887292816171758481508008183004141690689202014	130	UVM_INFO @ 16356939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				10 test runs
	csrng_stress_all_with_rand_reset	103462435036736544274968467433758804426918684566009028086170720477119283730459	None
	csrng_stress_all_with_rand_reset	93776641708811616676304679249559340041479216264307977001677546489205180469929	None
	csrng_stress_all_with_rand_reset	12923715516614311207426723552808728769855103142945081002108302240626368244206	None
	csrng_stress_all_with_rand_reset	17474964058644943984621155296099521074892511571333436533135846289262685938941	None
	csrng_stress_all_with_rand_reset	41313781215825316237287086586666342785846399063186911533326330557524577004176	None
	csrng_stress_all_with_rand_reset	106722611369572381356898202564448633948730659363995176006151488819795786829290	None
	csrng_stress_all_with_rand_reset	48916040226194975855351189990701432766347714591372427555789390424776024233627	None
	csrng_stress_all_with_rand_reset	115553715335632306780050659190363131188771999651902312605311746878436794964794	None
	csrng_stress_all_with_rand_reset	72476361745423173126335750077416329087622199118426483477248029550686882351301	None
	csrng_stress_all_with_rand_reset	55376220441597050513629777714197308406557003736738156424906605646539449989226	None
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq				4 test runs
	csrng_stress_all	37097409245610189952545833121299217314922460027576852490833052846222531822978	138	UVM_INFO @ 9332782608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	35686782496350957769198838145974283611537385093117556818112345886290855519578	171	UVM_INFO @ 24021723116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	16469180490488330732561889639748657064923319037633839004850112149603080897639	135	UVM_INFO @ 2465390634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	39628662894211891893839719870366306381265651139621791376394731975751857983091	140	UVM_INFO @ 840257011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:418) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits				3 test runs
	csrng_cmds	14671628846265123851926356735360164035434951066530718943878436423636331947364	133	UVM_INFO @ 93843856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	2611074542465129279936400279712752855324826783504894397045831487525831104514	133	UVM_INFO @ 93546422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	35456677992247718659970993012642276330611982673414971206300027898557381325986	133	UVM_INFO @ 912760290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert recov_alert triggered unexpectedly				1 test run
	csrng_cmds	107365792562543725280882149561917442931466982622248865708429352928334020971555	138	UVM_INFO @ 144701828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---