Simulation Results: dma

 
09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.10 %
  • code
  • 92.20 %
  • assert
  • 95.97 %
  • func
  • 79.13 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 9.000s 2018.558us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 9.000s 459.869us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 9.000s 316.858us 50 50 100.00
csr_hw_reset 5 5 100.00
dma_csr_hw_reset 2.000s 15.530us 5 5 100.00
csr_rw 20 20 100.00
dma_csr_rw 2.000s 45.700us 20 20 100.00
csr_bit_bash 5 5 100.00
dma_csr_bit_bash 19.000s 12308.149us 5 5 100.00
csr_aliasing 5 5 100.00
dma_csr_aliasing 9.000s 448.695us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 38.594us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
dma_csr_rw 2.000s 45.700us 20 20 100.00
dma_csr_aliasing 9.000s 448.695us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 116.000s 4647.812us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 958.000s 246143.485us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 1681.000s 602015.505us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 1681.000s 602015.505us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 958.000s 246143.485us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 669.000s 213483.758us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 1681.000s 602015.505us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 12.000s 735.703us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 352.000s 148253.118us 3 3 100.00
alert_test 50 50 100.00
dma_alert_test 2.000s 30.478us 50 50 100.00
intr_test 50 50 100.00
dma_intr_test 2.000s 15.939us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
dma_tl_errors 4.000s 561.781us 20 20 100.00
tl_d_illegal_access 20 20 100.00
dma_tl_errors 4.000s 561.781us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
dma_csr_hw_reset 2.000s 15.530us 5 5 100.00
dma_csr_rw 2.000s 45.700us 20 20 100.00
dma_csr_aliasing 9.000s 448.695us 5 5 100.00
dma_same_csr_outstanding 3.000s 388.998us 20 20 100.00
tl_d_partial_access 50 50 100.00
dma_csr_hw_reset 2.000s 15.530us 5 5 100.00
dma_csr_rw 2.000s 45.700us 20 20 100.00
dma_csr_aliasing 9.000s 448.695us 5 5 100.00
dma_same_csr_outstanding 3.000s 388.998us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 19.000s 197.506us 5 5 100.00
dma_generic_stress 669.000s 213483.758us 5 5 100.00
dma_handshake_stress 1681.000s 602015.505us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 12.000s 628.545us 15 15 100.00
tl_intg_err 25 25 100.00
dma_tl_intg_err 4.000s 1516.215us 20 20 100.00
dma_sec_cm 1.000s 20.896us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 162.000s 6777.362us 25 25 100.00
dma_longer_transfer 13.000s 2602.916us 5 5 100.00
dma_stress_all_with_rand_reset 4.000s 214.071us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 63791244566548965160114894701253395741498576542311527878393365910463066060364 95
UVM_INFO @ 214070611ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---