Simulation Results: edn/edn0

 
09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.86 %
  • code
  • 95.28 %
  • assert
  • 97.57 %
  • func
  • 58.74 %
  • block
  • 96.95 %
  • line
  • 98.68 %
  • branch
  • 93.23 %
  • toggle
  • 89.22 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.07%
V2S
99.57%
V3
88.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 2.000s 20.008us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 2.000s 25.988us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 2.000s 30.453us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 7.000s 886.885us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 2.000s 16.856us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 3.000s 118.481us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 2.000s 30.453us 20 20 100.00
edn_csr_aliasing 2.000s 16.856us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 81.000s 8743.998us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 81.000s 8743.998us 300 300 100.00
genbits 300 300 100.00
edn_genbits 81.000s 8743.998us 300 300 100.00
interrupts 50 50 100.00
edn_intr 2.000s 29.978us 50 50 100.00
alerts 200 200 100.00
edn_alert 3.000s 253.163us 200 200 100.00
errs 100 100 100.00
edn_err 3.000s 106.579us 100 100 100.00
disable 91 100 91.00
edn_disable 2.000s 10.219us 50 50 100.00
edn_disable_auto_req_mode 6.000s 500.000us 41 50 82.00
stress_all 50 50 100.00
edn_stress_all 10.000s 407.443us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 2.000s 26.398us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 3.000s 258.353us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 6.000s 117.583us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 6.000s 117.583us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 2.000s 25.988us 5 5 100.00
edn_csr_rw 2.000s 30.453us 20 20 100.00
edn_csr_aliasing 2.000s 16.856us 5 5 100.00
edn_same_csr_outstanding 3.000s 448.306us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 2.000s 25.988us 5 5 100.00
edn_csr_rw 2.000s 30.453us 20 20 100.00
edn_csr_aliasing 2.000s 16.856us 5 5 100.00
edn_same_csr_outstanding 3.000s 448.306us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 24 25 96.00
edn_sec_cm 11.000s 2242.604us 5 5 100.00
edn_tl_intg_err 4.000s 145.666us 19 20 95.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 2.000s 17.978us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 3.000s 253.163us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 11.000s 2242.604us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 11.000s 2242.604us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 11.000s 2242.604us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 11.000s 2242.604us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 3.000s 253.163us 200 200 100.00
edn_sec_cm 11.000s 2242.604us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 3.000s 253.163us 200 200 100.00
sec_cm_tile_link_bus_integrity 19 20 95.00
edn_tl_intg_err 4.000s 145.666us 19 20 95.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 44 50 88.00
edn_stress_all_with_rand_reset 160.000s 22454.170us 44 50 88.00

Error Messages

   Test seed line log context
UVM_FATAL (edn_scoreboard.sv:431) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 5 test runs
edn_disable_auto_req_mode 21783927697652674679079193995091352062014831238675221830681300975743776228361 103
UVM_INFO @ 32322783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 83729262610776899201706990916825134360042641662034027178817830075338734665496 103
UVM_INFO @ 19053258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 78422772326736877418150949571963178992822644522952215299278817484105629820504 103
UVM_INFO @ 40183297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 81758418306473365257399111997984005311976593096483167646363698081568837495707 103
UVM_INFO @ 12480313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 69222652962873579561535943111542309853840773131624388302177391168164947098782 103
UVM_INFO @ 12915270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
edn_disable_auto_req_mode 82488338670117079033412419577518683807161424150793649974098552413793528293521 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 112947896687510949420416220943694545148540686084834030053519993950363113569493 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 6748375931984432774119119509594926998795780211874261329999692804301542031429 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 68541091942455403783675494036252822130689585495790543423704565950054795280808 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
edn_stress_all_with_rand_reset 31489373742873958628135076954367874994391773200324965654889101969371035222304 231
UVM_INFO @ 2995276530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 64859315970076120193416999006637697825478658080951335037679404443232496173247 268
UVM_INFO @ 1720206616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 34919337995008484718527356706834329716609473304638214259440751790591784037253 229
UVM_INFO @ 1587131608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 75339540687282783028328884281521187473917526851019892136440832888665353713990 269
UVM_INFO @ 2386251686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1028) virtual_sequencer [edn_common_vseq] expect alert:fatal_alert to fire 1 test run
edn_tl_intg_err 15851903158163965376525009772783581266748436135190827372363849130671999861454 110
UVM_INFO @ 57999154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 105076326542576604472368740344899739435406760378204648169330598475435709188352 311
UVM_INFO @ 25837267851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1150) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
edn_stress_all_with_rand_reset 32735154734948449862551364419515281306105131879813758674884618521264491634329 135
UVM_INFO @ 340137961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---