Simulation Results: edn/edn1

 
09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.10 %
  • code
  • 95.71 %
  • assert
  • 97.14 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.00 %
  • toggle
  • 96.15 %
  • FSM
  • 94.32 %
Validation stages
V1
100.00%
V2
99.59%
V2S
100.00%
V3
74.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.110s 18.904us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.080s 17.467us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.130s 181.497us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.370s 520.825us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.490s 460.115us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.740s 79.009us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.130s 181.497us 20 20 100.00
edn_csr_aliasing 1.490s 460.115us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 88.860s 9123.908us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 88.860s 9123.908us 300 300 100.00
genbits 300 300 100.00
edn_genbits 88.860s 9123.908us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.210s 21.037us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.480s 32.818us 200 200 100.00
errs 100 100 100.00
edn_err 1.460s 399.563us 100 100 100.00
disable 96 100 96.00
edn_disable 1.040s 13.387us 50 50 100.00
edn_disable_auto_req_mode 7.680s 500.000us 46 50 92.00
stress_all 50 50 100.00
edn_stress_all 7.580s 659.590us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.200s 16.381us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.170s 33.585us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.670s 154.360us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.670s 154.360us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.080s 17.467us 5 5 100.00
edn_csr_rw 1.130s 181.497us 20 20 100.00
edn_csr_aliasing 1.490s 460.115us 5 5 100.00
edn_same_csr_outstanding 1.300s 90.760us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.080s 17.467us 5 5 100.00
edn_csr_rw 1.130s 181.497us 20 20 100.00
edn_csr_aliasing 1.490s 460.115us 5 5 100.00
edn_same_csr_outstanding 1.300s 90.760us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 3.770s 1312.735us 5 5 100.00
edn_tl_intg_err 2.590s 159.556us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.070s 50.438us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.480s 32.818us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.770s 1312.735us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.770s 1312.735us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 3.770s 1312.735us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 3.770s 1312.735us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.480s 32.818us 200 200 100.00
edn_sec_cm 3.770s 1312.735us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.480s 32.818us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.590s 159.556us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 37 50 74.00
edn_stress_all_with_rand_reset 161.910s 13748.594us 37 50 74.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 11 test runs
edn_stress_all_with_rand_reset 65966982051260746273942114751342389734530341600698485431928371391407201959423 320
UVM_INFO @ 2820293966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 7056768809628539673855871139654365692245329362537360967132340133259894671937 189
UVM_INFO @ 2109506848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 75518417422815324188071746453947125686268994306136277491760320794872023724293 239
UVM_INFO @ 2393755039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 91217033048338760388819821911959878545209692205904516055034187340652064056935 121
UVM_INFO @ 332284619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 73665500012180214460944658892405812229441346811508927737128763205717402211268 173
UVM_INFO @ 1582146061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 5001722192468039597902322083159371840558555193539880901604087405328587173969 147
UVM_INFO @ 1070812937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 63585458688441489669500741403489800789370095902768743466131870972593883819509 178
UVM_INFO @ 1325657167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 62718872450926464566420488604922225656867061746440312884798809102208810993475 198
UVM_INFO @ 1159976124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 114639637985812816099688641256741690831980015915632087904170617458105401895166 241
UVM_INFO @ 3231246902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 55889634439002090535478677203232167418881515338886591357806142703264057976826 163
UVM_INFO @ 1574648379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 35761722027865190304865313773979439461817060182266339495171280040386280194862 277
UVM_INFO @ 2541414894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
edn_disable_auto_req_mode 92704584300357876007293926704067465157998260452332084571847820098865871919499 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 72781492628835215590161612194238111470592562788048619505566328875673005598516 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 2 test runs
edn_disable_auto_req_mode 96439359749685073861845512412201816175335354121215505686001733574855365140318 88
UVM_INFO @ 33622498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 60436808759224316261375379693190332854888949471305971997922572248028174295465 88
UVM_INFO @ 33134338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 8471969678443732009143086049088888070509201783925073248794748444940257978215 289
UVM_INFO @ 13748594412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit 1 test run
edn_stress_all_with_rand_reset 80226491694878996474595345339196306242924572994009034879767651254204064987523 201
/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 88234798 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup