Simulation Results: gpio

 
09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.48 %
  • code
  • 92.60 %
  • assert
  • 96.84 %
  • func
  • 100.00 %
  • line
  • 99.89 %
  • branch
  • 98.38 %
  • cond
  • 95.54 %
  • toggle
  • 94.19 %
  • FSM
  • 75.00 %
Validation stages
V1
98.82%
V2
92.84%
V2S
100.00%
V3
41.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 200 200 100.00
gpio_smoke 2.300s 1006.151us 50 50 100.00
gpio_smoke_no_pullup_pulldown 2.210s 268.171us 50 50 100.00
gpio_smoke_en_cdc_prim 2.220s 245.221us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 2.060s 87.547us 50 50 100.00
csr_hw_reset 5 5 100.00
gpio_csr_hw_reset 1.100s 21.460us 5 5 100.00
csr_rw 20 20 100.00
gpio_csr_rw 1.210s 61.822us 20 20 100.00
csr_bit_bash 5 5 100.00
gpio_csr_bit_bash 8.360s 4639.181us 5 5 100.00
csr_aliasing 4 5 80.00
gpio_csr_aliasing 2.140s 194.296us 4 5 80.00
csr_mem_rw_with_rand_reset 18 20 90.00
gpio_csr_mem_rw_with_rand_reset 1.710s 29.776us 18 20 90.00
regwen_csr_and_corresponding_lockable_csr 24 25 96.00
gpio_csr_rw 1.210s 61.822us 20 20 100.00
gpio_csr_aliasing 2.140s 194.296us 4 5 80.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 100 100 100.00
gpio_random_dout_din 2.070s 36.458us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 2.120s 80.602us 50 50 100.00
out_in_regs_read_write 50 50 100.00
gpio_dout_din_regs_random_rw 1.540s 56.659us 50 50 100.00
gpio_interrupt_programming 50 50 100.00
gpio_intr_rand_pgm 2.230s 105.943us 50 50 100.00
random_interrupt_trigger 50 50 100.00
gpio_rand_intr_trigger 4.860s 252.696us 50 50 100.00
interrupt_and_noise_filter 50 50 100.00
gpio_intr_with_filter_rand_intr_event 5.520s 111.807us 50 50 100.00
noise_filter_stress 50 50 100.00
gpio_filter_stress 27.820s 6379.301us 50 50 100.00
regs_long_reads_and_writes 50 50 100.00
gpio_random_long_reg_writes_reg_reads 7.990s 300.045us 50 50 100.00
full_random 50 50 100.00
gpio_full_random 1.550s 74.397us 50 50 100.00
stress_all 4 50 8.00
gpio_stress_all 85.970s 8429.363us 4 50 8.00
alert_test 50 50 100.00
gpio_alert_test 0.930s 13.324us 50 50 100.00
intr_test 50 50 100.00
gpio_intr_test 0.980s 17.677us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
gpio_tl_errors 4.020s 319.530us 20 20 100.00
tl_d_illegal_access 20 20 100.00
gpio_tl_errors 4.020s 319.530us 20 20 100.00
tl_d_outstanding_access 48 50 96.00
gpio_csr_rw 1.210s 61.822us 20 20 100.00
gpio_same_csr_outstanding 1.660s 28.058us 19 20 95.00
gpio_csr_aliasing 2.140s 194.296us 4 5 80.00
gpio_csr_hw_reset 1.100s 21.460us 5 5 100.00
tl_d_partial_access 48 50 96.00
gpio_csr_rw 1.210s 61.822us 20 20 100.00
gpio_same_csr_outstanding 1.660s 28.058us 19 20 95.00
gpio_csr_aliasing 2.140s 194.296us 4 5 80.00
gpio_csr_hw_reset 1.100s 21.460us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
gpio_tl_intg_err 3.160s 191.554us 20 20 100.00
gpio_sec_cm 1.330s 793.559us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
gpio_tl_intg_err 3.160s 191.554us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 41 50 82.00
gpio_rand_straps 0.930s 27.365us 41 50 82.00
stress_all_with_rand_reset 0 50 0.00
gpio_stress_all_with_rand_reset 24.290s 1405.552us 0 50 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 50 50 100.00
gpio_inp_prd_cnt 0.930s 12.253us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (gpio_scoreboard.sv:248) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 55 test runs
gpio_stress_all 50642870042541302128288059881126427853739133511897492630818645770029831996829 75
UVM_INFO @ 2935440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 69781988639487405857873552048945561247867977094094915440900958666676470090902 1602
UVM_INFO @ 4534159507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 54621096630954192175782187939518780496227616786280266464522950221192760632738 528
UVM_INFO @ 3211527515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 99982905897563728954515838073616417806160053467194054046308702466386755590543 355
UVM_INFO @ 1059116334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 29915585304603580819562472530631155381416731149773271065878874310362109269321 75
UVM_INFO @ 5151931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 31330150848960083300361422197364630825431505182799096973906448585737528339292 695
UVM_INFO @ 702402938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 58619004328924013150050458412216332299003949643536301901248736822327725878454 1369
UVM_INFO @ 3428761942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 111302622141910818336229408118860693710620388549828251680259519658830023436377 79
UVM_INFO @ 466658036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 98593983182828469906888076969842227353440695246761507477521063271005176199048 1033
UVM_INFO @ 2288750305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 64259030972373205069312076176315463223874537123938410299328739146756732119114 75
UVM_INFO @ 3735380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 101286247717906396908099117207025798457791578128985682516058181032455481321176 1060
UVM_INFO @ 10011465191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 83227308311553898474927388015932384226692634399392309904631140014836643277651 401
UVM_INFO @ 1953203590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 101292338406845007244893298538505851346126887381662288693091342634696635455703 312
UVM_INFO @ 1516150368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 46609962593065186127062364168203582404653679046844501947654510291067526166350 821
UVM_INFO @ 582222822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 67949743075769697998363099191196298892416310483362042993835071740383451508755 323
UVM_INFO @ 350037060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 75635427163803903505032405338491421825395111332321230256689991135695540616781 75
UVM_INFO @ 6853413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 46756796098841380944940307320454178899318949256059702707569039938757195841342 560
UVM_INFO @ 2250426646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 87576896940628553745158272567853285900126488121048247940592664331121493476526 80
UVM_INFO @ 563736588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 37692691517128920265487990192240317237118023104458575320139804168867998227464 77
UVM_INFO @ 918433490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 100303103217662813322322061599914176703242184507744418579659527838620943613606 1665
UVM_INFO @ 5127812288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 13835752397700051874523576434949635836482137274502996883999491622567049952572 1323
UVM_INFO @ 3878352629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 90452248494045649287627987614485036251233837758993880422669627884637218513455 661
UVM_INFO @ 1301275925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 46570266223000402713653228991241012302071540414164799439900312232144232572432 299
UVM_INFO @ 4028204706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 21280289412691497188745578554431876994128163351612416615358003908220109428925 368
UVM_INFO @ 466534496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 106505892479803854395186788805672338134743113029102960489887606668218772405144 75
UVM_INFO @ 6116973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 88308855474652815389827366090513273499035310872271265134932085725594949965806 78
UVM_INFO @ 421224949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 97600127036296971699769655406369850755975723876804315903376469057576453946491 728
UVM_INFO @ 2489145422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 4086827420342591154130554184322788870335808077846953317650704381967939869359 75
UVM_INFO @ 5435390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 56906182966409837078390839647942463608335696361677392807528637263718942917739 111
UVM_INFO @ 1440162927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 1561407371017960736036701057907058304947898642988872583002932073736974663852 75
UVM_INFO @ 2866323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 51217321744114776683054138622058926744024122236604296767948547590921219387675 75
UVM_INFO @ 1879264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 71717665927593533654186280162602462797983636105647875515689330103296781911662 1445
UVM_INFO @ 4117563899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 113897061531802962340220187052641620364633731450044930506046934496536579063744 75
UVM_INFO @ 1014025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 5649358715616578345097959775341482291210689767187131228290803879850607546593 132
UVM_INFO @ 199979329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 64249343045533297496503486774245315428838614532670529134882435108266794211833 82
UVM_INFO @ 553421218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 1873537946132676544673333650312294508990117502388931988796189760558411964309 816
UVM_INFO @ 676222079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 4125375361968446289185982032314975914107530246830050748998553469445201239240 1077
UVM_INFO @ 3494031035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 33603269829479499333363672042328733768291954369620654284892846385346704254603 1272
UVM_INFO @ 20148902647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 86499107700852472374529080053465285654095638926369474934529553479778048842370 117
UVM_INFO @ 539614536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 38203223216406597776015482576970335082838364715736723358810677451004437104315 316
UVM_INFO @ 1566393295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 82170633641496091671330603493088862391841545796889318139953937766648925091063 387
UVM_INFO @ 883861810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 13909323574968467085571791565795853169094373887382482207067001540395141504253 501
UVM_INFO @ 533532694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 6771515092274212135348682039877124040068813035688658558223841914545851727446 75
UVM_INFO @ 1439712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 55929139771523504191504402581129220590312533706818528229879780884281040284823 535
UVM_INFO @ 1945875283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 16699631632364472295674121411446783606961963794423032857790638060007664142560 834
UVM_INFO @ 4882686160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 6903483882748402352969213945148915723833460295790371572263480465039322365176 75
UVM_INFO @ 1658234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 80510762607856400083105075683786059684121793381131754677818872339626866444857 1289
UVM_INFO @ 34621137177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 68051406981030375641498857721226841429719589649528238501388172754129127963804 1816
UVM_INFO @ 1637075466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 17097807124891591878646157687442202727168172730525185980225745586419495297225 493
UVM_INFO @ 1917989677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 22205338107895138690680029722187548643683996256064841548897115446807731157163 76
UVM_INFO @ 2093275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 40814680326557497868637808689344775225486055748001639603091142762923823621510 75
UVM_INFO @ 984178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 23314086408896745604370026604056229369998197706023518075703551566581312151077 546
UVM_INFO @ 481884133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 7641645724009123572857731802668224400959568449157369139599130104894657603254 1258
UVM_INFO @ 4126900607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 849522874387223187718189119291758596111409773143958868910064283553929820346 141
UVM_INFO @ 21780731400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 65802703509919626637094382691859317841861952823177436520528051822576400174333 386
UVM_INFO @ 400378807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [gpio_common_vseq] Check failed (vseq_done) 25 test runs
gpio_stress_all_with_rand_reset 65327384696386513607255202662114257949965102703361773878046157968105416446512 80
UVM_INFO @ 42899519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 48051001668439833165971194390412379616377941016642059688596247297790171795785 80
UVM_INFO @ 6822246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 43898265865658142596628509624475732206160018970735142610718546854457861478828 82
UVM_INFO @ 1848231025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 52360804003126632670151079322997610301208484556592372700079205141880924417986 81
UVM_INFO @ 826070937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 112164234872047769541283246648195205922441827045489015104499822040299430544006 80
UVM_INFO @ 6053995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 66341213239104458628370957911832259163912746443459197893786486085336321248776 189
UVM_INFO @ 1863263658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 103123635332856545567382569117383819194269489238243802502876670595955468460275 114
UVM_INFO @ 135527739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 100821750235302904318602993164567244715388657255770243930212342267077441151933 84
UVM_INFO @ 938054555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 113526270108202851326595107047907929897405598098085050417724137833391826558825 81
UVM_INFO @ 133596742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 57778163933861591747627287617884767300512892074256035791579686709721364850071 80
UVM_INFO @ 200151584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 41587229386420450677011293776292977391097020891713269734425609448271810286079 80
UVM_INFO @ 6625881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 47137305005212259872460151215088286331258123613389667339175908373268107212484 141
UVM_INFO @ 1194413438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 88267804037131248817023358097228359119644409000198923010858237894613586551708 81
UVM_INFO @ 202583286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 50353036064194959058715435279439205109164316928883595123206443663520303044455 80
UVM_INFO @ 40758091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 26447892617386272973557766785403386232763076291370335735178214067851407248399 83
UVM_INFO @ 628036871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 34427530535405806320543334540128132462163664250097201324356599550233009635884 81
UVM_INFO @ 205800606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 58722010946855047181762413203991505430960907967044730723028327972647575006046 85
UVM_INFO @ 16716767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 62599316646800667820472507061959572915111402219862941292332436120409623277036 80
UVM_INFO @ 6844014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 22427640237096607891303647737233081348346006129045154421604451341359992912501 80
UVM_INFO @ 166370570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 64166523673722322943685219487486296551457179465223547279486512275567685720662 82
UVM_INFO @ 2634458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 23895625324512541692456048050470135651941843531499137351589626612589714121075 80
UVM_INFO @ 2748168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 29638194742413727678090772321230209866113361915838210466237187944836903433555 80
UVM_INFO @ 57777546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 51961242557514942966738768216952249901618556254068847829427512248505805209095 179
UVM_INFO @ 519192044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 54705898277248728215482724398707014360147859871175548030447237637804162928228 344
UVM_INFO @ 256396043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 89540034403145292119061799582403704141552223701519864172425341204538858051072 85
UVM_INFO @ 10162235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 25 test runs
gpio_stress_all_with_rand_reset 67128599966659449775873008139571550998445672851013568887616227467295273119911 80
UVM_INFO @ 3586979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 114448372515878432521037096756326729299182359133188738399030740313556258658997 81
UVM_INFO @ 3950867019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 75814422333536830352745309368371123207259317302183611621239046880147021864130 191
UVM_INFO @ 425058833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 42025343591001303141328286288294129137340530894823301169765712617513150845326 97
UVM_INFO @ 1119711758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 38873469795769593903177692757756025004488088290924748305891814973363454546727 78
UVM_INFO @ 175498230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 100622502722269938704815267992553479651849333769933317166032259491934328940798 204
UVM_INFO @ 361842703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 8359132219380432038358683931838538536468474762694886581819358061367091131891 135
UVM_INFO @ 308761154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 101602364104118712625512887239862975556528116814365459745065968184323199527676 80
UVM_INFO @ 26981607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 81914482753268451516137791026385652680035493690275884087958617740718805111271 78
UVM_INFO @ 5217227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 77785773319995848810069145048366686682714577951106422341214782348815813764925 79
UVM_INFO @ 397336978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 100589387831910059347119464913113460533834494348349914645594699708564411324126 78
UVM_INFO @ 7461718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 52229534130587373055316433085152685888671111431985233298182945508723027192071 78
UVM_INFO @ 185002705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 73700831009700555070801334684355282787226715863913794662414759834426031322445 78
UVM_INFO @ 4883728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 96736723581657923765033086784421326073071764527653569596243378164320556832154 711
UVM_INFO @ 1405552107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 77271021356281780032984671800987549969878759458696053928147720329014774282118 78
UVM_INFO @ 25517460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 25723690721800624520232281015138845945179035816175556203382797475843978071547 78
UVM_INFO @ 6562966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 82789978571330449082020911943963016137097963889287258889040997630235192883198 78
UVM_INFO @ 4237496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 93626813661883326344584250995433917504974154117396830607935196236375178257185 79
UVM_INFO @ 219449857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 21941212475553004132301571944596805966242343758877273629326103878581518341504 168
UVM_INFO @ 63746351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 90493189176929080027982077913890831659746597021375671571257310339656279286926 78
UVM_INFO @ 10929926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 85000874549413269054559021546264443705002526351526582216308816548756247918868 81
UVM_INFO @ 1607874663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 59915577215379851270670566854590762606461372402086504668008739251485901332975 78
UVM_INFO @ 1620675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 22615132438427285986456463523789759321379986331694916524918069896783791577767 283
UVM_INFO @ 586790916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 79814712606961222057744553640927198871466473959862222003581436784054908316566 285
UVM_INFO @ 1815766339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 58233746421175264274673630800477678776286554617636187977326513149493785602921 81
UVM_INFO @ 223219769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
gpio_same_csr_outstanding 95526214525422367176400710710213563743985802808156587863001355658914666623849 77
UVM_INFO @ 30240549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_val_* reset value: * 1 test run
gpio_csr_aliasing 87492914593185123561138232199207141717416938654673852141879796523416035956868 77
UVM_INFO @ 528643747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_* reset value: * 1 test run
gpio_csr_mem_rw_with_rand_reset 28242648387757150987916611242183417214999434914138478670627449600037064457225 85
UVM_INFO @ 16120433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_*.enable reset value: * 1 test run
gpio_csr_mem_rw_with_rand_reset 95821016004588283941256693708167085279980027363360060606263648132793048142037 85
UVM_INFO @ 14779783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---