Simulation Results: hmac

 
09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.69 %
  • code
  • 96.11 %
  • assert
  • 96.95 %
  • func
  • 100.00 %
  • block
  • 97.69 %
  • line
  • 98.44 %
  • branch
  • 94.23 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
98.57%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 22.000s 1952.454us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 2.000s 158.114us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 3.000s 147.008us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 18.000s 26286.847us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 7.000s 4669.201us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 174.000s 25871.488us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 3.000s 147.008us 20 20 100.00
hmac_csr_aliasing 7.000s 4669.201us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 60.000s 969.042us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 95.000s 1620.450us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 329.000s 13456.359us 30 30 100.00
hmac_test_sha384_vectors 672.000s 15486.982us 75 75 100.00
hmac_test_sha512_vectors 617.000s 27851.461us 75 75 100.00
hmac_test_hmac256_vectors 21.000s 422.516us 50 50 100.00
hmac_test_hmac384_vectors 21.000s 450.025us 60 60 100.00
hmac_test_hmac512_vectors 29.000s 453.664us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 46.000s 7192.809us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 448.000s 41438.285us 10 10 100.00
error 10 10 100.00
hmac_error 109.000s 28389.687us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 133.000s 7827.434us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 22.000s 1952.454us 10 10 100.00
hmac_long_msg 60.000s 969.042us 10 10 100.00
hmac_back_pressure 95.000s 1620.450us 25 25 100.00
hmac_datapath_stress 448.000s 41438.285us 10 10 100.00
hmac_burst_wr 46.000s 7192.809us 50 50 100.00
hmac_stress_all 1286.000s 222883.162us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 22.000s 1952.454us 10 10 100.00
hmac_long_msg 60.000s 969.042us 10 10 100.00
hmac_back_pressure 95.000s 1620.450us 25 25 100.00
hmac_datapath_stress 448.000s 41438.285us 10 10 100.00
hmac_wipe_secret 133.000s 7827.434us 10 10 100.00
hmac_test_sha256_vectors 329.000s 13456.359us 30 30 100.00
hmac_test_sha384_vectors 672.000s 15486.982us 75 75 100.00
hmac_test_sha512_vectors 617.000s 27851.461us 75 75 100.00
hmac_test_hmac256_vectors 21.000s 422.516us 50 50 100.00
hmac_test_hmac384_vectors 21.000s 450.025us 60 60 100.00
hmac_test_hmac512_vectors 29.000s 453.664us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 22.000s 1952.454us 10 10 100.00
hmac_long_msg 60.000s 969.042us 10 10 100.00
hmac_back_pressure 95.000s 1620.450us 25 25 100.00
hmac_datapath_stress 448.000s 41438.285us 10 10 100.00
hmac_burst_wr 46.000s 7192.809us 50 50 100.00
hmac_error 109.000s 28389.687us 10 10 100.00
hmac_wipe_secret 133.000s 7827.434us 10 10 100.00
hmac_test_sha256_vectors 329.000s 13456.359us 30 30 100.00
hmac_test_sha384_vectors 672.000s 15486.982us 75 75 100.00
hmac_test_sha512_vectors 617.000s 27851.461us 75 75 100.00
hmac_test_hmac256_vectors 21.000s 422.516us 50 50 100.00
hmac_test_hmac384_vectors 21.000s 450.025us 60 60 100.00
hmac_test_hmac512_vectors 29.000s 453.664us 75 75 100.00
hmac_stress_all 1286.000s 222883.162us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1286.000s 222883.162us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 5.000s 12.990us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 2.000s 15.855us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 5.000s 867.702us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 5.000s 867.702us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 2.000s 158.114us 5 5 100.00
hmac_csr_rw 3.000s 147.008us 20 20 100.00
hmac_csr_aliasing 7.000s 4669.201us 5 5 100.00
hmac_same_csr_outstanding 4.000s 428.646us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 2.000s 158.114us 5 5 100.00
hmac_csr_rw 3.000s 147.008us 20 20 100.00
hmac_csr_aliasing 7.000s 4669.201us 5 5 100.00
hmac_same_csr_outstanding 4.000s 428.646us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 2.000s 193.240us 5 5 100.00
hmac_tl_intg_err 6.000s 536.780us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 6.000s 536.780us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 22.000s 1952.454us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.000s 775.640us 25 25 100.00
stress_all_with_rand_reset 34 35 97.14
hmac_stress_all_with_rand_reset 411.000s 142339.700us 34 35 97.14
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 57.036us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [hmac_common_vseq] wait timeout occurred! 1 test run
hmac_stress_all_with_rand_reset 74877556315762824164025328309664333888640170680200934228261237265509795597886 2107
UVM_INFO @ 11331746230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---