Simulation Results: kmac/unmasked

 
09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.61 %
  • code
  • 92.38 %
  • assert
  • 97.90 %
  • func
  • 96.54 %
  • line
  • 97.65 %
  • branch
  • 95.93 %
  • cond
  • 94.75 %
  • toggle
  • 100.00 %
  • FSM
  • 73.55 %
Validation stages
V1
100.00%
V2
97.92%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 73.670s 11804.056us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.390s 31.707us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.580s 152.637us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 15.630s 5667.400us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 7.500s 484.476us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.420s 332.475us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.580s 152.637us 20 20 100.00
kmac_csr_aliasing 7.500s 484.476us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.090s 16.025us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.950s 158.449us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 4115.060s 128728.324us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 955.410s 418352.435us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2143.390s 249087.920us 5 5 100.00
kmac_test_vectors_sha3_256 2453.230s 380661.695us 5 5 100.00
kmac_test_vectors_sha3_384 1408.140s 509093.213us 5 5 100.00
kmac_test_vectors_sha3_512 918.890s 46344.071us 5 5 100.00
kmac_test_vectors_shake_128 2828.300s 435897.258us 5 5 100.00
kmac_test_vectors_shake_256 1977.360s 61702.359us 5 5 100.00
kmac_test_vectors_kmac 3.020s 946.867us 5 5 100.00
kmac_test_vectors_kmac_xof 2.680s 263.635us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 376.180s 76005.906us 50 50 100.00
app 50 50 100.00
kmac_app 343.860s 80270.731us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 206.960s 12810.003us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 269.150s 150313.535us 50 50 100.00
error 49 50 98.00
kmac_error 396.200s 200000.000us 49 50 98.00
key_error 50 50 100.00
kmac_key_error 12.720s 4002.057us 50 50 100.00
sideload_invalid 35 50 70.00
kmac_sideload_invalid 122.590s 10034.293us 35 50 70.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 35.580s 501.426us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 40.710s 21228.120us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 62.170s 18486.258us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 35.660s 1812.972us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2482.920s 735683.145us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.220s 28.255us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.220s 21.604us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 5.230s 1923.378us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 5.230s 1923.378us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.390s 31.707us 5 5 100.00
kmac_csr_rw 1.580s 152.637us 20 20 100.00
kmac_csr_aliasing 7.500s 484.476us 5 5 100.00
kmac_same_csr_outstanding 3.280s 133.968us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.390s 31.707us 5 5 100.00
kmac_csr_rw 1.580s 152.637us 20 20 100.00
kmac_csr_aliasing 7.500s 484.476us 5 5 100.00
kmac_same_csr_outstanding 3.280s 133.968us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.640s 331.791us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.640s 331.791us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.640s 331.791us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.640s 331.791us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 4.860s 193.834us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_sec_cm 54.420s 9185.145us 5 5 100.00
kmac_tl_intg_err 4.700s 256.123us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 4.700s 256.123us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 35.660s 1812.972us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 73.670s 11804.056us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 376.180s 76005.906us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.640s 331.791us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 54.420s 9185.145us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 54.420s 9185.145us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 54.420s 9185.145us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 73.670s 11804.056us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 35.660s 1812.972us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 54.420s 9185.145us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 291.240s 106908.788us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 73.670s 11804.056us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
kmac_stress_all_with_rand_reset 364.540s 5788.977us 4 10 40.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) 6 test runs
kmac_sideload_invalid 95048446085601400020132127629806990101094226889084334484626253648780124687353 78
UVM_INFO @ 10008989161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 18051726980682749035027872886517690671932127098705893055577790776322031861928 78
UVM_INFO @ 10009575059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 23553763129620410928946811065659302569099232327698633204852539553228423125018 78
UVM_INFO @ 10035935729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 75683403095042776500159602725558031505688597019448505304782662954022995932570 78
UVM_INFO @ 10017642479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 21238037598470548468455171781794568384147759587729309214932383119987608532362 78
UVM_INFO @ 10033239545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 10545495701583251558029578785052496460010295005503827904850893409612368781229 78
UVM_INFO @ 10018932292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 3 test runs
kmac_stress_all_with_rand_reset 37189691465430950855200228759552486724672627226844893585989169378297056395496 221
UVM_INFO @ 13349810573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 49429463908887610824630205849536485935856642225099546373791605639024530258021 194
UVM_INFO @ 486223307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 70148057028711820353323358348650321402202500407673760076486323956160161143746 394
UVM_INFO @ 20298135912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
kmac_stress_all_with_rand_reset 10566216030765013508476408173133641869158715148821219005063729011368884777593 179
UVM_INFO @ 15101632801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 105561573170116733710141579338261981788182801918290641958673197243556254599776 339
UVM_INFO @ 11330290289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 55633869542467391776965278289006649868397490388693236153963588620914351718618 159
UVM_INFO @ 30216663803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) 1 test run
kmac_sideload_invalid 10143921086553091208358273832016770658039448020680454303557162865988172705580 110
UVM_INFO @ 10188599494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) 1 test run
kmac_sideload_invalid 53900003938788148189740247703387438333644522448460958247931686880461954965210 86
UVM_INFO @ 10096457357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) 1 test run
kmac_sideload_invalid 16007978926981540080313103375770464164789374907877346533848782607135162787132 96
UVM_INFO @ 10131708322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) 1 test run
kmac_sideload_invalid 26741728408045533178195914445280922746766174751547134568636179364463115126174 89
UVM_INFO @ 10277434543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) 1 test run
kmac_sideload_invalid 107092032675818705479171535895627532248182390194430318509160033416533654765 94
UVM_INFO @ 10493245536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) 1 test run
kmac_sideload_invalid 27804399566052506801165391046745475986345446019969419128101059756142940088126 87
UVM_INFO @ 10090754126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) 1 test run
kmac_sideload_invalid 73790819217621762526031812434165120711544113389578501554347963290794397546775 84
UVM_INFO @ 10075929197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) 1 test run
kmac_sideload_invalid 18816070846911694086082108716970303066637524781233952904464958539420677406251 80
UVM_INFO @ 10034293412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
kmac_error 85306574028338281207606902687893819878365058058039416272471596395000832165485 237
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) 1 test run
kmac_sideload_invalid 77436457361363219269959909941845583922878509070190173556749284496308125879180 81
UVM_INFO @ 10179547329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---