Simulation Results: lc_ctrl/volatile_unlock_enabled

 
09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.46 %
  • code
  • 94.59 %
  • assert
  • 95.97 %
  • func
  • 89.81 %
  • block
  • 97.25 %
  • line
  • 97.72 %
  • branch
  • 93.02 %
  • toggle
  • 89.99 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
99.59%
V2S
100.00%
V3
32.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 6.000s 110.783us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 2.000s 15.715us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 2.000s 47.704us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 2.000s 68.011us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 52.248us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 22.259us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 2.000s 47.704us 20 20 100.00
lc_ctrl_csr_aliasing 2.000s 52.248us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 4.000s 376.693us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 15.000s 1551.926us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 2.000s 14.347us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 5.000s 279.775us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 8.000s 555.787us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 13.000s 6370.240us 50 50 100.00
security_escalation 258 260 99.23
lc_ctrl_state_failure 8.000s 555.787us 50 50 100.00
lc_ctrl_prog_failure 5.000s 279.775us 50 50 100.00
lc_ctrl_errors 13.000s 6370.240us 50 50 100.00
lc_ctrl_security_escalation 10.000s 488.058us 50 50 100.00
lc_ctrl_jtag_state_failure 59.000s 3937.237us 19 20 95.00
lc_ctrl_jtag_prog_failure 14.000s 2095.242us 19 20 95.00
lc_ctrl_jtag_errors 58.000s 21049.434us 20 20 100.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 10.000s 2037.568us 20 20 100.00
lc_ctrl_jtag_state_post_trans 18.000s 1116.503us 20 20 100.00
lc_ctrl_jtag_prog_failure 14.000s 2095.242us 19 20 95.00
lc_ctrl_jtag_errors 58.000s 21049.434us 20 20 100.00
lc_ctrl_jtag_access 21.000s 6486.880us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 21.000s 2947.901us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 963.451us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.000s 468.681us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 26.000s 7776.575us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 8.000s 286.704us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 159.211us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 129.815us 10 10 100.00
lc_ctrl_jtag_alert_test 3.000s 219.242us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 15.000s 8613.474us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 59.761us 50 50 100.00
stress_all 49 50 98.00
lc_ctrl_stress_all 425.000s 21774.339us 49 50 98.00
alert_test 50 50 100.00
lc_ctrl_alert_test 3.000s 39.307us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 5.000s 147.466us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 5.000s 147.466us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 2.000s 15.715us 5 5 100.00
lc_ctrl_csr_rw 2.000s 47.704us 20 20 100.00
lc_ctrl_csr_aliasing 2.000s 52.248us 5 5 100.00
lc_ctrl_same_csr_outstanding 3.000s 48.513us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 2.000s 15.715us 5 5 100.00
lc_ctrl_csr_rw 2.000s 47.704us 20 20 100.00
lc_ctrl_csr_aliasing 2.000s 52.248us 5 5 100.00
lc_ctrl_same_csr_outstanding 3.000s 48.513us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 5.000s 1107.777us 5 5 100.00
lc_ctrl_tl_intg_err 4.000s 445.757us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 4.000s 445.757us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 15.000s 1551.926us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 8.000s 555.787us 50 50 100.00
lc_ctrl_sec_cm 5.000s 1107.777us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 8.000s 555.787us 50 50 100.00
lc_ctrl_sec_cm 5.000s 1107.777us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 8.000s 555.787us 50 50 100.00
lc_ctrl_sec_cm 5.000s 1107.777us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 8.000s 555.787us 50 50 100.00
lc_ctrl_sec_cm 5.000s 1107.777us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 8.000s 555.787us 50 50 100.00
lc_ctrl_sec_cm 5.000s 1107.777us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 8.000s 555.787us 50 50 100.00
lc_ctrl_sec_cm 5.000s 1107.777us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 8.000s 555.787us 50 50 100.00
lc_ctrl_sec_cm 5.000s 1107.777us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 8.000s 555.787us 50 50 100.00
lc_ctrl_sec_cm 5.000s 1107.777us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 10.000s 488.058us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 4.000s 376.693us 50 50 100.00
lc_ctrl_jtag_state_post_trans 18.000s 1116.503us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 14.000s 666.373us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 14.000s 666.373us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 16.000s 1206.043us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 9.000s 3469.338us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 9.000s 3469.338us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 16 50 32.00
lc_ctrl_stress_all_with_rand_reset 90.000s 14145.364us 16 50 32.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 32 test runs
lc_ctrl_stress_all_with_rand_reset 26748744842468340693320283906156156518641756831197301684603706397948229474567 341
UVM_INFO @ 2967413165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 111241971946085232375162811896715326469011546101218525867644189619074734487437 161
UVM_INFO @ 116350085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 108099662235617181903025352765055685431369486328415319352899827229223779715201 3928
UVM_INFO @ 4461142752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 91821036205209521680179787301107079351414823027358105216994729490532353274121 160
UVM_INFO @ 128087975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 103257204356669395434668132098499234070087067862741146733276263220860672308512 911
UVM_INFO @ 10455261337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 14641180383343048436058738248055680047542540123054267865381455550639361980217 1737
UVM_INFO @ 1148704283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 13513210163469167254523253871288471815872346219629293196290236375002897529637 192
UVM_INFO @ 1733368801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 93496973334470348279180591686819157474161254514573169845957936083433357333228 161
UVM_INFO @ 103999618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 81765652601404259745500356126647517904490925689556892099725756841979254607726 3325
UVM_INFO @ 2219692765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 80922995243950887952018859632127566360265912664331051808537061737025883214535 2465
UVM_INFO @ 9327843381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 1108099458816629637257178901974222470001436421781654893132327662979877958979 444
UVM_INFO @ 808814629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 89287674792179182289414999569437545731330512244994751177256259663416285636043 1083
UVM_INFO @ 2063997807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 12734112673883896594650024404977128510132397595798497622204810109940423273601 303
UVM_INFO @ 540896919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 34500072377045875909774460479381788649015244528100563927037043501856113527318 259
UVM_INFO @ 3222259587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 55905192714814562504126988244797016674306387639934148497481889420055227325041 1032
UVM_INFO @ 5987740506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 9249327583252949042922594276162851043367943795248850199915123995415200909191 170
UVM_INFO @ 2628132129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 22886916631454405760977863994186384628714018340497884855562071245957579303948 543
UVM_INFO @ 2083027753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 8872941730073235621811962126019003887383656922879212249289835455305427386307 166
UVM_INFO @ 2295263664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 29646664301887560343443981589821075985878359463067617957440191585958806458860 416
UVM_INFO @ 3545290463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 51863828184341858323002923259690263425988182752755744199829853857179145643568 191
UVM_INFO @ 3132656519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 82230695332581538730544710057548801381165183161026205582144585407252827263540 2424
UVM_INFO @ 6164265273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 5554383402870209137517688370370427355123163651847920606009656050183764526655 164
UVM_INFO @ 1397113584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 105370813981639332318467915173241539332532397955549243440796111679325894567774 2639
UVM_INFO @ 14145363574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 100698025414857020940016391690901235436947570276262413101139887611552219158910 7989
UVM_INFO @ 6693355346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 59131024095138575363031901456147883258617490851605121019227892329574604908440 170
UVM_INFO @ 110441415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 12844508959403131414727180582891817172081618012616571911685168710349358147128 745
UVM_INFO @ 2807797541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 69638492316653692434583013795740788161345363954001254347157656273530764694823 409
UVM_INFO @ 4439966934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 40977424369043939226962715092095865350607736892280707296861601879254575223651 1090
UVM_INFO @ 10735731008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 34392549309551323890175113132065724144809955009963264161955329208635873480512 160
UVM_INFO @ 694959173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 47232031588656053203901728788646225107121656636977394905895910443869777370715 445
UVM_INFO @ 12252063129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 60742297310789294292777830774413309658064275248953439212310288177993755958243 1473
UVM_INFO @ 2442403863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 50201416204208678573754717594700041302037736661199975645563947274607895207459 840
UVM_INFO @ 5297963270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 2 test runs
lc_ctrl_stress_all_with_rand_reset 101252723432221903093025384705741778882725698109495754964517406718582733798254 1505
UVM_INFO @ 1367114769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 34996253875569391488812419905357478429534612951394177003408008619745214195297 2989
UVM_INFO @ 11976521655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 1 test run
lc_ctrl_jtag_prog_failure 31383376774406316598382314463008417020415859451974722431398780249846880682257 177
UVM_INFO @ 72873220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_failure 110543641823628758185410900280176664818717433908484473874552175162059978887702 180
UVM_INFO @ 271978028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* 1 test run
lc_ctrl_stress_all 89292066585858659457610469517966392795325260848960287432923493695410690258617 4222
UVM_INFO @ 3825066444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---