Simulation Results: otbn

 
09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.94 %
  • code
  • 96.77 %
  • assert
  • 97.06 %
  • func
  • 100.00 %
  • block
  • 99.53 %
  • line
  • 99.63 %
  • branch
  • 94.10 %
  • toggle
  • 93.33 %
  • FSM
  • 100.00 %
Validation stages
V1
99.40%
V2
99.64%
V2S
97.94%
V3
20.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 12.000s 42.525us 1 1 100.00
single_binary 99 100 99.00
otbn_single 60.000s 880.173us 99 100 99.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 10.000s 47.386us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 7.000s 44.835us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 11.000s 95.249us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 8.000s 60.901us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 14.000s 77.232us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 7.000s 44.835us 20 20 100.00
otbn_csr_aliasing 8.000s 60.901us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 124.000s 5230.274us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 54.000s 8491.185us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 53.000s 149.582us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 63.000s 591.997us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 76.000s 1000.750us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 196.000s 611.488us 10 10 100.00
lc_escalation 60 60 100.00
otbn_escalate 22.000s 115.196us 60 60 100.00
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 8.000s 50.998us 5 5 100.00
sw_errs_fatal_chk 9 10 90.00
otbn_sw_errs_fatal_chk 27.000s 75.434us 9 10 90.00
alert_test 50 50 100.00
otbn_alert_test 9.000s 33.870us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 7.000s 38.274us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 9.000s 62.378us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 9.000s 62.378us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 10.000s 47.386us 5 5 100.00
otbn_csr_rw 7.000s 44.835us 20 20 100.00
otbn_csr_aliasing 8.000s 60.901us 5 5 100.00
otbn_same_csr_outstanding 8.000s 91.924us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 10.000s 47.386us 5 5 100.00
otbn_csr_rw 7.000s 44.835us 20 20 100.00
otbn_csr_aliasing 8.000s 60.901us 5 5 100.00
otbn_same_csr_outstanding 8.000s 91.924us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 10.000s 59.893us 10 10 100.00
otbn_dmem_err 70.000s 687.606us 15 15 100.00
internal_integrity 14 17 82.35
otbn_alu_bignum_mod_err 22.000s 147.414us 4 5 80.00
otbn_controller_ispr_rdata_err 10.000s 111.233us 4 5 80.00
otbn_mac_bignum_acc_err 10.000s 56.798us 4 5 80.00
otbn_urnd_err 12.000s 37.577us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 7.000s 77.823us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 7.000s 23.393us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 13.000s 61.763us 10 10 100.00
tl_intg_err 25 25 100.00
otbn_sec_cm 285.000s 5455.490us 5 5 100.00
otbn_tl_intg_err 31.000s 1211.794us 20 20 100.00
passthru_mem_tl_intg_err 18 20 90.00
otbn_passthru_mem_tl_intg_err 113.000s 496.020us 18 20 90.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 285.000s 5455.490us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 285.000s 5455.490us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 12.000s 42.525us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 70.000s 687.606us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 10.000s 59.893us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 31.000s 1211.794us 20 20 100.00
sec_cm_controller_fsm_global_esc 60 60 100.00
otbn_escalate 22.000s 115.196us 60 60 100.00
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 10.000s 59.893us 10 10 100.00
otbn_dmem_err 70.000s 687.606us 15 15 100.00
otbn_zero_state_err_urnd 8.000s 50.998us 5 5 100.00
otbn_illegal_mem_acc 7.000s 77.823us 5 5 100.00
otbn_sec_cm 285.000s 5455.490us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 285.000s 5455.490us 5 5 100.00
sec_cm_scramble_key_sideload 99 100 99.00
otbn_single 60.000s 880.173us 99 100 99.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 10.000s 59.893us 10 10 100.00
otbn_dmem_err 70.000s 687.606us 15 15 100.00
otbn_zero_state_err_urnd 8.000s 50.998us 5 5 100.00
otbn_illegal_mem_acc 7.000s 77.823us 5 5 100.00
otbn_sec_cm 285.000s 5455.490us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 285.000s 5455.490us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 60 60 100.00
otbn_escalate 22.000s 115.196us 60 60 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 10.000s 59.893us 10 10 100.00
otbn_dmem_err 70.000s 687.606us 15 15 100.00
otbn_zero_state_err_urnd 8.000s 50.998us 5 5 100.00
otbn_illegal_mem_acc 7.000s 77.823us 5 5 100.00
otbn_sec_cm 285.000s 5455.490us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 285.000s 5455.490us 5 5 100.00
sec_cm_data_reg_sw_sca 99 100 99.00
otbn_single 60.000s 880.173us 99 100 99.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 12.000s 40.877us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 10.000s 49.409us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 60.000s 142.241us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 60.000s 142.241us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 19.000s 285.365us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 285.000s 5455.490us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 285.000s 5455.490us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 9 10 90.00
otbn_rf_bignum_intg_err 11.000s 126.284us 9 10 90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 285.000s 5455.490us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 285.000s 5455.490us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 65.000s 286.066us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 65.000s 286.066us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 22.000s 100.306us 7 7 100.00
sec_cm_data_mem_sec_wipe 99 100 99.00
otbn_single 60.000s 880.173us 99 100 99.00
sec_cm_instruction_mem_sec_wipe 99 100 99.00
otbn_single 60.000s 880.173us 99 100 99.00
sec_cm_data_reg_sw_sec_wipe 99 100 99.00
otbn_single 60.000s 880.173us 99 100 99.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 76.000s 1000.750us 10 10 100.00
sec_cm_ctrl_flow_count 99 100 99.00
otbn_single 60.000s 880.173us 99 100 99.00
sec_cm_ctrl_flow_sca 99 100 99.00
otbn_single 60.000s 880.173us 99 100 99.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 44.000s 153.432us 5 5 100.00
sec_cm_key_sideload 99 100 99.00
otbn_single 60.000s 880.173us 99 100 99.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 285.000s 5455.490us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
otbn_stress_all_with_rand_reset 639.000s 8509.864us 2 10 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 41.231us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
otbn_stress_all_with_rand_reset 92164300435965486015510568887081215561943435099438617075901431011699956618701 268
UVM_INFO @ 3284328416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 109475240883028348204388029785042865404024695427586944800385690072945659547787 193
UVM_INFO @ 755968674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 30819376786559631853450378192325885853971330288901886599492590154780493129705 217
UVM_INFO @ 1193137915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 68986122703917355758421591600697352252999741615219943702539735022631640628855 192
UVM_INFO @ 1103325920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 4 test runs
otbn_mac_bignum_acc_err 67699334852796869815434269081430897508122131068820950607333814322072992414700 120
UVM_INFO @ 43201973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_alu_bignum_mod_err 7668991631862994669443897067583186073182842824863231910915761621027846511820 117
UVM_INFO @ 53008907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_controller_ispr_rdata_err 1592423374322925356128367057925033972858539540999464159996341325186432417168 109
UVM_INFO @ 111232641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 43647336862875488707918829064379131581353092771772622112787305645233681064496 112
UVM_INFO @ 81565029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 3 test runs
otbn_stress_all_with_rand_reset 48577127097715453810856600457929349585228485882700408449368242055871105704108 844
UVM_INFO @ 3884981003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 87682146788773562933970528346621999708044379866552944449518714335593335932671 165
UVM_INFO @ 221846601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 53037474257776472999065228853950444689489015069352718706720638970553920117885 346
UVM_INFO @ 1340747314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 2 test runs
otbn_passthru_mem_tl_intg_err 50354642888727793530528402943707337925684903036502036849912489883083654619510 106
UVM_INFO @ 82163615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_single 85079642601399288816930521741374313553239797163996756633573819584992551920895 107
UVM_INFO @ 53672094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1028) virtual_sequencer [otbn_sw_errs_fatal_chk_vseq] expect alert:fatal to fire 1 test run
otbn_sw_errs_fatal_chk 49599958794943632934526167603728470234262900115936201765492672318285079470574 109
UVM_INFO @ 142116603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 10713791532725575670245247163861253983250353126398962319528879338997081888243 402
UVM_INFO @ 4674640821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 112691545470531595066028904378914565920106829694135455856390602768845494637 91
UVM_INFO @ 27508771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---