| V1 |
|
100.00% |
| V2 |
|
100.00% |
| unmapped |
|
85.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prim_alert_request_test | 80 | 80 | 100.00 | |||
| prim_async_alert | 0.610s | 11.680us | 20 | 20 | 100.00 | |
| prim_async_fatal_alert | 0.650s | 33.238us | 20 | 20 | 100.00 | |
| prim_sync_alert | 0.560s | 9.014us | 20 | 20 | 100.00 | |
| prim_sync_fatal_alert | 0.650s | 28.723us | 20 | 20 | 100.00 | |
| prim_alert_test | 80 | 80 | 100.00 | |||
| prim_async_alert | 0.610s | 11.680us | 20 | 20 | 100.00 | |
| prim_async_fatal_alert | 0.650s | 33.238us | 20 | 20 | 100.00 | |
| prim_sync_alert | 0.560s | 9.014us | 20 | 20 | 100.00 | |
| prim_sync_fatal_alert | 0.650s | 28.723us | 20 | 20 | 100.00 | |
| prim_alert_ping_request_test | 80 | 80 | 100.00 | |||
| prim_async_alert | 0.610s | 11.680us | 20 | 20 | 100.00 | |
| prim_async_fatal_alert | 0.650s | 33.238us | 20 | 20 | 100.00 | |
| prim_sync_alert | 0.560s | 9.014us | 20 | 20 | 100.00 | |
| prim_sync_fatal_alert | 0.650s | 28.723us | 20 | 20 | 100.00 | |
| prim_alert_integrity_errors_test | 80 | 80 | 100.00 | |||
| prim_async_alert | 0.610s | 11.680us | 20 | 20 | 100.00 | |
| prim_async_fatal_alert | 0.650s | 33.238us | 20 | 20 | 100.00 | |
| prim_sync_alert | 0.560s | 9.014us | 20 | 20 | 100.00 | |
| prim_sync_fatal_alert | 0.650s | 28.723us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prim_alert_init_trigger_test | 80 | 80 | 100.00 | |||
| prim_async_alert | 0.610s | 11.680us | 20 | 20 | 100.00 | |
| prim_async_fatal_alert | 0.650s | 33.238us | 20 | 20 | 100.00 | |
| prim_sync_alert | 0.560s | 9.014us | 20 | 20 | 100.00 | |
| prim_sync_fatal_alert | 0.650s | 28.723us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 17 | 20 | 85.00 | |||
| prim_async_fatal_alert_with_3_cycles_skew | 0.580s | 29.736us | 17 | 20 | 85.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Offending 'alert_o' | 3 test runs | |||
| prim_async_fatal_alert_with_3_cycles_skew | 42467899325959452095647453037178389236514585407330786826966055956106588729037 | 100 |
UVM_ERROR src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv(320) @ 30758000: reporter [ASSERT FAILED] Alert_A
Starting assertion attempts at time 30828236ps: level = 0 arg = i_alert_receiver.PingDiffOk_A (from inst prim_alert_tb (src/lowrisc_dv_prim_alert_sim_0.1/tb/prim_alert_tb.sv:254))
[prim_alert_seq] Ping signal integrity error sequence finished!
|
|
| prim_async_fatal_alert_with_3_cycles_skew | 98274705151002522862742474854569188354408282583273962421323508137998111384479 | 100 |
UVM_ERROR src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv(320) @ 30921000: reporter [ASSERT FAILED] Alert_A
Starting assertion attempts at time 30990739ps: level = 0 arg = i_alert_receiver.PingDiffOk_A (from inst prim_alert_tb (src/lowrisc_dv_prim_alert_sim_0.1/tb/prim_alert_tb.sv:254))
[prim_alert_seq] Ping signal integrity error sequence finished!
|
|
| prim_async_fatal_alert_with_3_cycles_skew | 47368309208528415642224954498504956852213662440658402120642794161319826000646 | 100 |
UVM_ERROR src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv(320) @ 31355000: reporter [ASSERT FAILED] Alert_A
Starting assertion attempts at time 31415393ps: level = 0 arg = i_alert_receiver.PingDiffOk_A (from inst prim_alert_tb (src/lowrisc_dv_prim_alert_sim_0.1/tb/prim_alert_tb.sv:254))
[prim_alert_seq] Ping signal integrity error sequence finished!
|
|