Simulation Results: rom_ctrl/32kb

 
09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.90 %
  • code
  • 94.61 %
  • assert
  • 96.79 %
  • func
  • 99.29 %
  • block
  • 96.73 %
  • line
  • 97.22 %
  • branch
  • 94.09 %
  • toggle
  • 87.12 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
97.10%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 5.000s 142.394us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 6.000s 133.714us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 6.000s 131.354us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 5.000s 554.570us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 7.000s 372.426us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.000s 600.507us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 6.000s 131.354us 20 20 100.00
rom_ctrl_csr_aliasing 7.000s 372.426us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 5.000s 388.323us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 5.000s 627.977us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 5.000s 555.446us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 19.000s 3675.964us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 7.000s 970.991us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 8.000s 164.758us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 8.000s 536.939us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 8.000s 536.939us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 6.000s 133.714us 5 5 100.00
rom_ctrl_csr_rw 6.000s 131.354us 20 20 100.00
rom_ctrl_csr_aliasing 7.000s 372.426us 5 5 100.00
rom_ctrl_same_csr_outstanding 5.000s 538.896us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 6.000s 133.714us 5 5 100.00
rom_ctrl_csr_rw 6.000s 131.354us 20 20 100.00
rom_ctrl_csr_aliasing 7.000s 372.426us 5 5 100.00
rom_ctrl_same_csr_outstanding 5.000s 538.896us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 10029.201us 18 20 90.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.000s 3692.524us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 119.000s 956.012us 5 5 100.00
rom_ctrl_tl_intg_err 32.000s 1505.255us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 119.000s 956.012us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 119.000s 956.012us 5 5 100.00
sec_cm_checker_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 10029.201us 18 20 90.00
sec_cm_checker_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 10029.201us 18 20 90.00
sec_cm_checker_fsm_local_esc 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 10029.201us 18 20 90.00
sec_cm_compare_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 10029.201us 18 20 90.00
sec_cm_compare_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 10029.201us 18 20 90.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 119.000s 956.012us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 119.000s 956.012us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 5.000s 142.394us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 5.000s 142.394us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 5.000s 142.394us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 32.000s 1505.255us 20 20 100.00
sec_cm_bus_local_esc 20 22 90.91
rom_ctrl_corrupt_sig_fatal_chk 54.000s 10029.201us 18 20 90.00
rom_ctrl_kmac_err_chk 7.000s 970.991us 2 2 100.00
sec_cm_mux_mubi 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 10029.201us 18 20 90.00
sec_cm_mux_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 10029.201us 18 20 90.00
sec_cm_ctrl_redun 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 54.000s 10029.201us 18 20 90.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.000s 3692.524us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 119.000s 956.012us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 18 20 90.00
rom_ctrl_stress_all_with_rand_reset 138.000s 10681.484us 18 20 90.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 2 test runs
rom_ctrl_stress_all_with_rand_reset 115649515280894868104067521987551389453611110273892874291911686290032899165786 91
UVM_INFO @ 1197408697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 76927978196093372703916928312565116554218418273808540101296004511169672080610 91
UVM_INFO @ 360561856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 2 test runs
rom_ctrl_corrupt_sig_fatal_chk 17712662276456692928428813733307581042626049943243170703832208864708470850011 94
UVM_INFO @ 876371645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 71116473739302223598046138785435948710890920762961733182856274329682943603926 94
UVM_INFO @ 8450913171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---