Simulation Results: rom_ctrl/64kb

 
09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.93 %
  • code
  • 94.55 %
  • assert
  • 96.94 %
  • func
  • 99.29 %
  • block
  • 96.63 %
  • line
  • 97.22 %
  • branch
  • 93.82 %
  • toggle
  • 87.16 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
85.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 7.000s 2554.209us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 9.000s 717.771us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 8.000s 302.925us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 7.000s 1029.251us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 6.000s 1685.503us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 8.000s 328.671us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 8.000s 302.925us 20 20 100.00
rom_ctrl_csr_aliasing 6.000s 1685.503us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 7.000s 217.932us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 6.000s 227.324us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 7.000s 712.335us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 31.000s 4783.214us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 13.000s 933.395us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 9.000s 295.874us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 10.000s 535.011us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 10.000s 535.011us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 9.000s 717.771us 5 5 100.00
rom_ctrl_csr_rw 8.000s 302.925us 20 20 100.00
rom_ctrl_csr_aliasing 6.000s 1685.503us 5 5 100.00
rom_ctrl_same_csr_outstanding 9.000s 710.524us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 9.000s 717.771us 5 5 100.00
rom_ctrl_csr_rw 8.000s 302.925us 20 20 100.00
rom_ctrl_csr_aliasing 6.000s 1685.503us 5 5 100.00
rom_ctrl_same_csr_outstanding 9.000s 710.524us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.000s 92801.873us 20 20 100.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.000s 3157.047us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 213.000s 566.977us 5 5 100.00
rom_ctrl_tl_intg_err 61.000s 913.428us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 213.000s 566.977us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 213.000s 566.977us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.000s 92801.873us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.000s 92801.873us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.000s 92801.873us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.000s 92801.873us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.000s 92801.873us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 213.000s 566.977us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 213.000s 566.977us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 7.000s 2554.209us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 7.000s 2554.209us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 7.000s 2554.209us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 61.000s 913.428us 20 20 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.000s 92801.873us 20 20 100.00
rom_ctrl_kmac_err_chk 13.000s 933.395us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.000s 92801.873us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.000s 92801.873us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 148.000s 92801.873us 20 20 100.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.000s 3157.047us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 213.000s 566.977us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 17 20 85.00
rom_ctrl_stress_all_with_rand_reset 132.000s 11756.333us 17 20 85.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 3 test runs
rom_ctrl_stress_all_with_rand_reset 77594903922791572196502720592252841426704603464183443096637314626101370472998 91
UVM_INFO @ 426301318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 98332456106078659126227698834719932802161132699675951468180417593233037417948 91
UVM_INFO @ 334062274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 114307788485338154456510437597449356294905884216870765299069321967956589499626 93
UVM_INFO @ 2560964757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---