Simulation Results

Simulation Results: rv_dm/use_dmi_interface

09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.39 %

code
84.86 %

assert
96.43 %

func
98.89 %

block
94.12 %

line
94.74 %

branch
84.10 %

toggle
80.25 %

FSM
80.36 %

Validation stages

V1		98.89%
V2		55.12%
V2S		91.11%
V3		10.00%
unmapped		0.00%

178/180 passed

98.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	38.000s	1572.518us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	41.000s	144.593us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	47.000s	129.396us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	63.000s	14967.718us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	38.000s	1030.210us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	50.000s	9086.481us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	55.000s	15238.977us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	190.000s	101316.327us	20	20	100.00
jtag_dmi_csr_aliasing				5	5	100.00
	rv_dm_jtag_dmi_csr_aliasing	107.000s	87781.059us	5	5	100.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	41.000s	362.133us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	46.000s	976.809us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	43.000s	626.984us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	42.000s	371.686us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	38.000s	296.314us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	43.000s	1489.497us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	49.000s	310.409us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	49.000s	661.423us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	41.000s	362.133us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	42.000s	214.058us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	44.000s	217.743us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	43.000s	626.984us	2	2	100.00
rom_read_access				2	2	100.00
	rv_dm_rom_read_access	48.000s	152.921us	2	2	100.00
csr_hw_reset				5	5	100.00
	rv_dm_csr_hw_reset	40.000s	100.911us	5	5	100.00
csr_rw				20	20	100.00
	rv_dm_csr_rw	47.000s	368.839us	20	20	100.00
csr_bit_bash				5	5	100.00
	rv_dm_csr_bit_bash	84.000s	25236.510us	5	5	100.00
csr_aliasing				5	5	100.00
	rv_dm_csr_aliasing	79.000s	20840.944us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rv_dm_csr_mem_rw_with_rand_reset	47.000s	177.486us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rv_dm_csr_aliasing	79.000s	20840.944us	5	5	100.00
	rv_dm_csr_rw	47.000s	368.839us	20	20	100.00
mem_walk				5	5	100.00
	rv_dm_mem_walk	39.000s	112.085us	5	5	100.00
mem_partial_access				5	5	100.00
	rv_dm_mem_partial_access	48.000s	160.396us	5	5	100.00

156/283 passed

55.12 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	38.000s	1572.518us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	44.000s	795.347us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	41.000s	700.534us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	36.000s	726.987us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	53.000s	1086.456us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	53.000s	6595.826us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	55.000s	3061.867us	0	20	0.00
bad_sba				3	20	15.00
	rv_dm_bad_sba_tl_access	61.000s	8442.635us	3	20	15.00
sba_autoincrement				3	20	15.00
	rv_dm_autoincr_sba_tl_access	111.000s	40832.136us	3	20	15.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	48.000s	525.672us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	40.000s	614.450us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	48.000s	803.920us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	49.000s	41.965us	0	5	0.00
tap_ctrl_transitions				11	11	100.00
	rv_dm_tap_fsm	45.000s	6722.733us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	105.000s	14142.218us	10	10	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	52.000s	97.913us	1	1	100.00
stress_all				4	50	8.00
	rv_dm_stress_all	10801.000s	0.000us	4	50	8.00
alert_test				50	50	100.00
	rv_dm_alert_test	48.000s	151.573us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rv_dm_tl_errors	48.000s	354.325us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rv_dm_tl_errors	48.000s	354.325us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rv_dm_csr_aliasing	79.000s	20840.944us	5	5	100.00
	rv_dm_csr_hw_reset	40.000s	100.911us	5	5	100.00
	rv_dm_csr_rw	47.000s	368.839us	20	20	100.00
	rv_dm_same_csr_outstanding	53.000s	6759.404us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rv_dm_csr_aliasing	79.000s	20840.944us	5	5	100.00
	rv_dm_csr_hw_reset	40.000s	100.911us	5	5	100.00
	rv_dm_csr_rw	47.000s	368.839us	20	20	100.00
	rv_dm_same_csr_outstanding	53.000s	6759.404us	20	20	100.00

V2S

41/45 passed

91.11 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				24	25	96.00
	rv_dm_sec_cm	50.000s	1359.865us	5	5	100.00
	rv_dm_tl_intg_err	58.000s	4046.943us	19	20	95.00
sec_cm_bus_integrity				19	20	95.00
	rv_dm_tl_intg_err	58.000s	4046.943us	19	20	95.00
sec_cm_lc_hw_debug_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	40.000s	614.450us	2	2	100.00
	rv_dm_debug_disabled	40.000s	75.021us	2	2	100.00
sec_cm_lc_dft_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	40.000s	614.450us	2	2	100.00
	rv_dm_debug_disabled	40.000s	75.021us	2	2	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	38.000s	1572.518us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				7	10	70.00
	rv_dm_buffered_enable	46.000s	250.947us	7	10	70.00
sec_cm_sba_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	48.000s	54.169us	4	4	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	48.000s	54.169us	4	4	100.00
sec_cm_exec_ctrl_mubi				7	10	70.00
	rv_dm_buffered_enable	46.000s	250.947us	7	10	70.00

1/10 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	10	10.00
	rv_dm_stress_all_with_rand_reset	55.000s	1001.582us	1	10	10.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	825.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				42 test runs
	rv_dm_sba_tl_access	47310705652704137767643585478585263390794299034011443921002593664755320383013	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24243
	rv_dm_autoincr_sba_tl_access	36456973028000136005985380380783217538632605927782623861384895516729066904647	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24119
	rv_dm_sba_tl_access	22588936402328297867678018202687166734004118184143172080123024387861170166233	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24203
	rv_dm_bad_sba_tl_access	24124110480689523150523048895144096131672899170539867825584300885383385241918	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @16159
	rv_dm_sba_tl_access	113812386524831232800095528502105216317411790639866797756457598000923301624807	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24211
	rv_dm_delayed_resp_sba_tl_access	114179524199711417103429288325855608497644703544882914282651946776357060932792	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24106
	rv_dm_sba_tl_access	54033642459593214704901426239590458246791496617280201531857893944774828612583	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24194
	rv_dm_bad_sba_tl_access	68617562399509766454883586625870804978932576654837916302994717544006743086775	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24145
	rv_dm_sba_tl_access	48412877698783618756496947796670078165696724664187528310813911832263182585912	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24259
	rv_dm_bad_sba_tl_access	55769634936863022099378655244050020399188092171378162375113972392103544603531	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24273
	rv_dm_autoincr_sba_tl_access	46252142241654474191003092575196710634632309681581097067525740363156083335758	108	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24346
	rv_dm_sba_tl_access	114725101527858145980858159264198601315028472932501280828483662005817417748111	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24168
	rv_dm_bad_sba_tl_access	15443264951825121531102111240819724843132412947874819848786574537879445099787	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24186
	rv_dm_autoincr_sba_tl_access	78293323605345881418118622263617544963343296020830126016758366458939751277971	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24164
	rv_dm_sba_tl_access	50336337439584743282299421296188771328408323622892195169959566269117045126208	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24247
	rv_dm_autoincr_sba_tl_access	27833807858617660953362461520416308558439758927568734029839551403764984258298	105	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24289
	rv_dm_sba_tl_access	18308813946946878354908282346791284534911527209308783764710762814003570100370	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24242
	rv_dm_bad_sba_tl_access	107354737557520038668627383780241964815965486982108006034305935178517799755656	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24199
	rv_dm_sba_tl_access	87493646667175769556607515229007146255514904081653977182200604458508334696569	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24193
	rv_dm_bad_sba_tl_access	283760965495532530364440916452935344934156364273499626100198441430043005456	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24348
	rv_dm_sba_tl_access	37910939220778854703832258235892983454544785834775422399079187118764763226076	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24165
	rv_dm_bad_sba_tl_access	47820982554996677612586709159086706606023100280068412738039470869775295487378	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24246
	rv_dm_autoincr_sba_tl_access	97239356634223715427905844333623371085084224094670012276065717910073289915639	153	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24452
	rv_dm_sba_tl_access	14316136998812814641477915029862496228878886050263061264138098366353093911367	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24250
	rv_dm_autoincr_sba_tl_access	33747943151882204924278455776227279671097704946214176806874382896096741494882	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24748
	rv_dm_sba_tl_access	25356811069429547346486604499187116068294694243703661148119615576568882664345	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24199
	rv_dm_bad_sba_tl_access	103093323383975688073273498655844475993721885849317676966292304295653083440464	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24246
	rv_dm_autoincr_sba_tl_access	71423765338173234663754991855031695392873805666364656133181698160831457895558	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24117
	rv_dm_sba_tl_access	32719265331195149738936508374868248568243120364502701771346549661099311314631	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24166
	rv_dm_sba_tl_access	66376738035514295167133803316370008437780897205153781774015538404640515907985	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24246
	rv_dm_bad_sba_tl_access	26319848183200452770372067548736326299844967470127053655143180982351066308117	114	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24297
	rv_dm_sba_tl_access	50797764332426827130134989097505023988318286886544752303044933219183719930104	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24186
	rv_dm_bad_sba_tl_access	80851776032098015325068061270333473220131406815630545695260699858338180660009	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24442
	rv_dm_autoincr_sba_tl_access	90208228870443441677472467364132385587036223525738563409935477975598452005237	135	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24368
	rv_dm_sba_tl_access	22053729812297364426032782018498633851214956241958369897903954143606670789461	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24320
	rv_dm_autoincr_sba_tl_access	38861438947614678971879980558822073852581936454170925195693717760807132171680	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24206
	rv_dm_sba_tl_access	30904979977318931981015330394980572175750658190448259550669024828941858579996	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24248
	rv_dm_sba_tl_access	2607733655120332510936331585288193033815328949365324470535429394636808856740	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24200
	rv_dm_autoincr_sba_tl_access	88718203927001586655947892284222890302575588735398697196490248719506344281877	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24241
	rv_dm_sba_tl_access	54153671823572919727056613230555115813473630651585861155127515249168122529223	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24251
	rv_dm_sba_tl_access	19378952048164699282611217961941156380061197480665129335313885267029776224195	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24196
	rv_dm_bad_sba_tl_access	71468210617708700084029875711366978320113114649522565382817249305251943436303	105	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24346
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				32 test runs
	rv_dm_delayed_resp_sba_tl_access	41969894277768595236334766174509794380610156813693422577168451621948893939502	107	UVM_INFO @ 521405625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	81934298389508631317551289571972410454961813928515175876332030950682153408686	107	UVM_INFO @ 54005803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	54092561556826624817532852870668965538399870638938143417477026222088073674770	107	UVM_INFO @ 60226688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	20733350524925663658092512504136168153665149881131832876950446518503447293405	107	UVM_INFO @ 103673853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	25778128635736738583014496572421564385143890721061617898611405211524971659405	119	UVM_INFO @ 8442635248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	52257923342315220299476033283291090551857753117963825808016694694265955221401	107	UVM_INFO @ 282026979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	46245392821796734649100909592684043972567225714947877265348894566459168516143	107	UVM_INFO @ 150795737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	17030407057699538495937282407785883577211112359958601110558904451352794446556	107	UVM_INFO @ 107690185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	113467395793786072080187960180509464922316698503626230843223694830720090755028	107	UVM_INFO @ 166687958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	48262796969371120837880261227431087260126122048263107428229600581614930262751	107	UVM_INFO @ 90386898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	29386468147998664566017583507380250755544137715366301458326031343528881842290	107	UVM_INFO @ 85002976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	33804882085649737618957028285950440373026796612367318597868907987354752712081	113	UVM_INFO @ 3143033565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	79890318446261645177100236463963030843549731260736494312015164958041365070662	107	UVM_INFO @ 167756415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	94010194006886365017460389187966616723707897858539545249109113359688780866822	107	UVM_INFO @ 39008725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	31012597667842434896308223393379088560923271467458642491775079852909635256626	107	UVM_INFO @ 62026501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	24119241776784502992970044402374476764127678900228519975834783044663101278181	107	UVM_INFO @ 58613277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	36665101572870268164814081138376054122349526001872870522324528761259776506219	107	UVM_INFO @ 736839792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	26891828028411082607663607970360392498049751793079619936404448466285922359172	107	UVM_INFO @ 125057172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	104514538437383217339965922420125530793853843202863728999156924440226796542430	107	UVM_INFO @ 62450156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	66474759264609664892920455660867923309052683913505251861975502138836855595802	107	UVM_INFO @ 466803894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	52584969305116466256645803482249295958394912209681244893022624686662926034691	107	UVM_INFO @ 290174968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	65844063408702420473484690132323198762542041217379004711984640090034759565754	122	UVM_INFO @ 1814558372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	100158469780717851255034445049395686775287965221709553061684544150805593421743	107	UVM_INFO @ 145532926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	52997165190437667086317078493397463257336028841686112887169192725496747089935	107	UVM_INFO @ 54484722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	99272848338458274138759272950705487371673254061940280714255739703479614645213	107	UVM_INFO @ 75601938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	1600971394495467226877323238563277566348541340924213057197103409552732839746	107	UVM_INFO @ 255236242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	72665158288093954470545701420884519955999713119901821235675490081841002728318	107	UVM_INFO @ 36117188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	114718385574088480157263589411014112722654075097612922753101439504853130655244	107	UVM_INFO @ 64520935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	73406750310642989182349851029097002080333037810025104108956007188345937413220	107	UVM_INFO @ 709754341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	67197749366787988587422623190517502724429163101711803234493628617020311595195	107	UVM_INFO @ 187116380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	47529674393041647314890292211916864668647823562383527241365608214788899659491	107	UVM_INFO @ 85252690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	108317634465235961112951761237725349123451221352504670240381708719270075098818	107	UVM_INFO @ 70959517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				20 test runs
	rv_dm_hart_unavail	98083311273978752564368417217019897863030240816850639157955815356563050978875	87	UVM_INFO @ 261385888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	89719620011630539295996363062537976688340109365409144116776943879370094427613	91	UVM_INFO @ 5778120210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	3956287463420312442135718014757127102603428249232703351492371244571664687130	87	UVM_INFO @ 41965231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	12500305021698315094184157139393088830672162060138694892410293263875632575106	87	UVM_INFO @ 102256372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	1367402721076454762178482493914557303028463155013401100137132064187900279930	91	UVM_INFO @ 3594114656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	16090552790157933459421524281828422998198684230768248515461204106697894057117	98	UVM_INFO @ 551543309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	10178513055592424288149734036435442129078307618975552764635842172086701842906	87	UVM_INFO @ 62845888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	92257499219337418688406910285196346925335351637460999810575503769391585474133	87	UVM_INFO @ 45433365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	113556920238905538868280428967150812193290670671517319611032705009830608047695	98	UVM_INFO @ 1314040739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	110407829752430630561080824872202858895162140181804086053260222741937903890797	88	UVM_INFO @ 128537018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	72163288749054512015505817350718160216697636005067243650735517175442300898044	88	UVM_INFO @ 291703361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	43553531280651984032013687191930714015614703654471586603901580735355309326306	90	UVM_INFO @ 1974464656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	111205467536072726858834851638689265064019899022994733573737754410360793821980	91	UVM_INFO @ 761217958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	72256230657809494759220519538619341498485836392600100977158807148084077496575	90	UVM_INFO @ 880449286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	78617857252231864387949228441264736551748837978524628787516767688612268492072	88	UVM_INFO @ 191367741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	80178534468506171736300237604121592031113100485814315031867720185552194389866	88	UVM_INFO @ 287435950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	52226080436354663021891508791758274020601694476399275877557145025610732744633	88	UVM_INFO @ 124012200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	11616366217758748608316244573537906034671446272279030947100506455917500944026	89	UVM_INFO @ 700607774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	91279477804717151590427156357893480238550864497876611080516773179039142558081	91	UVM_INFO @ 1304323544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	14628660479379094660114556041432320439716480359774175714894318966457911416768	88	UVM_INFO @ 71506189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				17 test runs
	rv_dm_jtag_dmi_debug_disabled	85262068118647885085921826186431308412737175957710055161514991506998709334220	87	UVM_INFO @ 525672156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	80093433124510903020552223049670467030185789325112732736332818867189483074614	87	UVM_INFO @ 261081964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	105611349525402686167485646901644719720098400807038281517968524961187876780428	89	UVM_INFO @ 328401854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	69124308347276599789139445401450069556825930174119822991141264897989860324173	126	UVM_INFO @ 5307646373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	25486866368872493326526461548210695771109233467041290932814028391238775241787	90	UVM_INFO @ 1021209484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	100232086647176300066925823469911795592246164228357606864189190149979336646618	88	UVM_INFO @ 470308106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	60279123254158500685919854837693824775600901296887133551235580831647547625430	92	UVM_INFO @ 1207238322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	30169904348413636947175338547305873102222381402271442637074171501326446569570	91	UVM_INFO @ 2960022643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	3229509074194909657777555816828491983185022664984945259030237981052625214973	92	UVM_INFO @ 916640364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	9091561162355677212375279442488980145307842932515544646286127918469828794377	90	UVM_INFO @ 690613135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	46190857131551540604346701708554450694378056557015624815346698372106588061373	89	UVM_INFO @ 437807891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	36343402455833792823717753948812836969242316895228836525365034245130515552487	89	UVM_INFO @ 695654773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	67121208757379279094299587099125454085322439112082971360129646830741150924139	88	UVM_INFO @ 601291938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	46634734524326889346215300012683776711079773127807057540100951577139232397054	91	UVM_INFO @ 1443617505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	55416223399557189644295446555272052526079622368951694471163196065325921110216	88	UVM_INFO @ 329112466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	47657734338996747161736347858465960932417030775106645063369434323136258111772	89	UVM_INFO @ 273522061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	12217212291259629474677528756177043828035884932457678679994484449639894216215	93	UVM_INFO @ 3051518588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				14 test runs
	rv_dm_mem_tl_access_resuming	109564446559065696424181376315234233649982036102898644715667170400406558309607	87	UVM_INFO @ 143431330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	41761343652475831361375166315286690751535321920108304985604376191247529509495	95	UVM_INFO @ 600206761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	5205119344313570773554895497227144608964682964818966741174839931404815479728	87	UVM_INFO @ 371686040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	1004522565602683606312034355017887095869878060761866963438942727280022827053	95	UVM_INFO @ 4548703123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	19627905171218203749963586743583352964022880610973877004824390901482909631880	89	UVM_INFO @ 1570516260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	47170873261607024124240457282819531327116908222738836018493713075225615867154	92	UVM_INFO @ 1066582046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	79619988038652456354831692421034322311761819102502136642539207997698779190175	92	UVM_INFO @ 686084674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	22915442992117052278932340058037956570035957811735473648150795717375260017630	88	UVM_INFO @ 624849700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	23064532310349503654120734082878684594946643320270112876805806983931967823825	88	UVM_INFO @ 97400124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	24064832607184799873894975033716054951165477414589477241408965163396685566689	94	UVM_INFO @ 11789450489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	98506462862757362948335254446299630941091209744222761140873610959706466889370	90	UVM_INFO @ 850114835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	106227677585896442008674334240889895246087483982009689586780934944493048039424	89	UVM_INFO @ 489902004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	89733421769544559640883824570690280808330271256041416548422486280165121021761	92	UVM_INFO @ 2467190452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	98387175375705913359515853079762810041050579941172246870935768979756522237492	88	UVM_INFO @ 280411287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				7 test runs
	rv_dm_scanmode	49177631951433790792181927239319918763977241661134305285331251781201450068884	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	43951986731328571292858797644007719886485377473541996678855794062004395165041	93	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	66734903068581232493293196886147596356221081646069507394304737244187919716265	89	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	103287559307053914365755859439456346208547030536619803648724474283914217843916	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	33371825107922531547868026351458657377846518367362233183020220570210475493533	92	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	29431448780666699599260172493525841417811112644089955944803786576173967269670	90	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	51315598151883595064219071061748893362547426355363747924688502441518454512978	89	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_dm_common_vseq] Check failed (vseq_done)				4 test runs
	rv_dm_stress_all_with_rand_reset	83563721453027106042535616593393422392535396285400791848929181439064184892139	101	UVM_INFO @ 2587479807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	92267670804234705494332834316644899799462957324459361405533882350623986727322	117	UVM_INFO @ 939651076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	72976850465088643974324765903348554564057530225531767373627812118780212584854	110	UVM_INFO @ 1001582164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	45518047850799561746169692749587213565939658147821128964952862347980694902536	101	UVM_INFO @ 3326244149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])				3 test runs
	rv_dm_buffered_enable	46943016614960777747735059281478296480927599429256860421428482576712178976725	90	UVM_INFO @ 258516867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	31965548356596170420852549751561772657125557956849798128145056470518444134979	89	UVM_INFO @ 250946686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	22791434780430029028232095854036756685850361236530904525485973263297756572190	92	UVM_INFO @ 222131402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				3 test runs
	rv_dm_stress_all	9955588762740327295789390333800479981438384013961889800813420513718621360345	None
	rv_dm_stress_all	79692244613781958489950598613739572495836762396112150660958250058028883442326	None
	rv_dm_stress_all	24304374675848940289995599912070679585876295055566630211981150324770863063009	None
UVM_ERROR (cip_base_vseq.sv:1028) virtual_sequencer [rv_dm_common_vseq] expect alert:fatal_fault to fire				1 test run
	rv_dm_tl_intg_err	52595919167015378316095848053101744873713758368002567287139335347154880912278	92	UVM_INFO @ 192187239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---