Simulation Results: rv_timer

 
09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.46 %
  • code
  • 95.85 %
  • assert
  • 96.52 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
92.50%
V2S
100.00%
V3
37.50%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 4.000s 960.353us 20 20 100.00
csr_hw_reset 5 5 100.00
rv_timer_csr_hw_reset 2.000s 12.655us 5 5 100.00
csr_rw 20 20 100.00
rv_timer_csr_rw 2.000s 29.521us 20 20 100.00
csr_bit_bash 5 5 100.00
rv_timer_csr_bit_bash 3.000s 1701.340us 5 5 100.00
csr_aliasing 5 5 100.00
rv_timer_csr_aliasing 2.000s 100.686us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 21.078us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rv_timer_csr_rw 2.000s 29.521us 20 20 100.00
rv_timer_csr_aliasing 2.000s 100.686us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 2 20 10.00
rv_timer_random_reset 3.000s 929.517us 2 20 10.00
disabled 20 20 100.00
rv_timer_disabled 4.000s 3674.433us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 722.000s 1375663.743us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 722.000s 1375663.743us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 8.000s 4360.404us 20 20 100.00
alert_test 50 50 100.00
rv_timer_alert_test 2.000s 13.785us 50 50 100.00
intr_test 50 50 100.00
rv_timer_intr_test 2.000s 44.152us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rv_timer_tl_errors 3.000s 318.369us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rv_timer_tl_errors 3.000s 318.369us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rv_timer_csr_hw_reset 2.000s 12.655us 5 5 100.00
rv_timer_csr_rw 2.000s 29.521us 20 20 100.00
rv_timer_csr_aliasing 2.000s 100.686us 5 5 100.00
rv_timer_same_csr_outstanding 2.000s 44.324us 20 20 100.00
tl_d_partial_access 50 50 100.00
rv_timer_csr_hw_reset 2.000s 12.655us 5 5 100.00
rv_timer_csr_rw 2.000s 29.521us 20 20 100.00
rv_timer_csr_aliasing 2.000s 100.686us 5 5 100.00
rv_timer_same_csr_outstanding 2.000s 44.324us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rv_timer_sec_cm 2.000s 92.366us 5 5 100.00
rv_timer_tl_intg_err 2.000s 43.907us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
rv_timer_tl_intg_err 2.000s 43.907us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 5 10 50.00
rv_timer_min 6.000s 1686.425us 5 10 50.00
max_value 0 10 0.00
rv_timer_max 2.000s 124.055us 0 10 0.00
stress_all_with_rand_reset 10 20 50.00
rv_timer_stress_all_with_rand_reset 59.000s 10784.439us 10 20 50.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 23 test runs
rv_timer_min 66182742917160473937385186129751341583019284851675744411746568731570566253579 85
UVM_INFO @ 82964811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 2461340102143650730612691059821641231661150091463975776503152479721946336241 85
UVM_INFO @ 120549552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 89762333616626157134623665195009239890154617299876757836093428400028259406844 85
UVM_INFO @ 200613589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 16633454640116406105941930028004327513545574069922884370808525769932215808077 84
UVM_INFO @ 113149673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 44519731483095860035213260199610133886079803938811318955009128742293702039597 84
UVM_INFO @ 67309499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 88729343428137139449642494285687891063005852255766716419243195830215422674413 85
UVM_INFO @ 372352042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 104202933951728024215379246853805976111722015329413777544900354530697202338641 85
UVM_INFO @ 1091406595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 51257666975848120371672476869566785470103481816519226988701152315724905120302 85
UVM_INFO @ 233926276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 47684365708528540091448419903784232121270484531146595130020444591582212609934 84
UVM_INFO @ 929517414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 61942196135486070921702534531202000915688251407123610552655079722039269979512 84
UVM_INFO @ 129897336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 29350364457287232864872209723583874639513904355891141219616518649307911434491 86
UVM_INFO @ 104899507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 50393620601125699037786202283603986102980981585470582344882317115684450955754 86
UVM_INFO @ 253363278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 46257716705629273684419966280860246262514718068144870022179951118750102010770 84
UVM_INFO @ 1686424748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 72434447574493572260976022887137625060850384584503585229816030241044818788243 86
UVM_INFO @ 185933195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 51407119197261085871191603809287969005834306972066697979590448719037343626523 85
UVM_INFO @ 126350617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 42785681954609474995678205365475829315389983378120372482625787489764357402920 84
UVM_INFO @ 897392599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 37113733652429560413545024413184059580378774403979871974608091162101043265657 85
UVM_INFO @ 111736427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 99853924334419436805727743929925413494327984662288266043083656711285302710360 84
UVM_INFO @ 519766176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 88432775585277815031860722471962383844868158544899345874548220628134875530630 84
UVM_INFO @ 1089768336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 28465179198159222026203191559714345503123759041194815068062613656913413195968 85
UVM_INFO @ 1161385507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 20546676174646331157519502589581327733797194271752527922768835137910981142913 84
UVM_INFO @ 304864840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 11813811204705347517325814131939920046342273760801207931535550110098903432249 84
UVM_INFO @ 278828962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 45554281537874389365693005338006942461197622027437947506685683905979406735824 87
UVM_INFO @ 484953091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 10 test runs
rv_timer_max 82150192854985267472879402006385596660114860896510610951000036025316920798424 84
UVM_INFO @ 43050241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 72445994292016333110232640262128160202825231314463817854659017345292015339190 84
UVM_INFO @ 44704604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 86098850552950798967842188274427286977304665833437245287061783795005051517383 84
UVM_INFO @ 326973333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 25746526456118289577784575141946068093688655838229516450403183700085876624864 84
UVM_INFO @ 303749421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 111198413696261688301713034237682514777550443315073544988623152321317705345765 84
UVM_INFO @ 88150425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 80963465893004324958403676658426774857683841952037115937070614752469739327751 84
UVM_INFO @ 49612715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 4417336557085850614232547682537211706436715366559381052966242404339648737006 85
UVM_INFO @ 175988890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 30046924692910910012163552777927950313868281396094982069083076769563989872101 84
UVM_INFO @ 45386878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 108670845496261152674954941534841525694096002202187932905001185206297604009124 84
UVM_INFO @ 124054597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 94794507953628207753604824533827986152487284939604077319738807345201886793013 84
UVM_INFO @ 228665779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) 6 test runs
rv_timer_stress_all_with_rand_reset 13675485007929999636545575940073444619831982580638906108122819196097834356934 174
UVM_INFO @ 2074007512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 112302115945785270505630952398444274364608267859656426447682542599122685744651 117
UVM_INFO @ 33026840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 69125552646406808605031477872725800691210948659869415747656678084438750120671 187
UVM_INFO @ 1942988881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 51905650502651865952614661094628508933061370011278889325798978844293949047044 119
UVM_INFO @ 2486682581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 91863610453596797535046363584768084214331898161993680239250046251140209759942 166
UVM_INFO @ 2803131161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 26815805483202335611425571447600280848019823567958471884951124497711947448749 143
UVM_INFO @ 389129082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 4 test runs
rv_timer_stress_all_with_rand_reset 62844725308661256764756077003322948722610727061218493098653487789860364793338 145
UVM_INFO @ 31602705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 42101301630286060822007445041838837056896619281142883706794477623793609678741 140
UVM_INFO @ 761143335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 88116442661459072344202387731507211082691550264742771964425810437323403386640 241
UVM_INFO @ 10091723806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 77963466467397858020075554602117866964085489211396023711959133110106218822764 354
UVM_INFO @ 9652303182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---