Simulation Results

Simulation Results: spi_host

09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.81 %

code
95.03 %

assert
95.64 %

func
90.76 %

block
96.96 %

line
98.76 %

branch
93.35 %

toggle
88.02 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		99.61%
V2S		100.00%
unmapped		100.00%

115/115 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	spi_host_smoke	89.000s	2297.850us	50	50	100.00
csr_hw_reset				5	5	100.00
	spi_host_csr_hw_reset	2.000s	22.354us	5	5	100.00
csr_rw				20	20	100.00
	spi_host_csr_rw	2.000s	20.288us	20	20	100.00
csr_bit_bash				5	5	100.00
	spi_host_csr_bit_bash	4.000s	616.028us	5	5	100.00
csr_aliasing				5	5	100.00
	spi_host_csr_aliasing	2.000s	50.626us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	spi_host_csr_mem_rw_with_rand_reset	2.000s	34.005us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	spi_host_csr_rw	2.000s	20.288us	20	20	100.00
	spi_host_csr_aliasing	2.000s	50.626us	5	5	100.00
mem_walk				5	5	100.00
	spi_host_mem_walk	1.000s	21.282us	5	5	100.00
mem_partial_access				5	5	100.00
	spi_host_mem_partial_access	1.000s	47.744us	5	5	100.00

767/770 passed

99.61 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
performance				50	50	100.00
	spi_host_performance	2.000s	118.694us	50	50	100.00
error_event_intr				150	150	100.00
	spi_host_overflow_underflow	58.000s	5915.741us	50	50	100.00
	spi_host_error_cmd	2.000s	29.612us	50	50	100.00
	spi_host_event	63.000s	1455.117us	50	50	100.00
clock_rate				49	50	98.00
	spi_host_speed	111.000s	200000.000us	49	50	98.00
speed				49	50	98.00
	spi_host_speed	111.000s	200000.000us	49	50	98.00
chip_select_timing				49	50	98.00
	spi_host_speed	111.000s	200000.000us	49	50	98.00
sw_reset				50	50	100.00
	spi_host_sw_reset	75.000s	2251.018us	50	50	100.00
passthrough_mode				50	50	100.00
	spi_host_passthrough_mode	2.000s	95.023us	50	50	100.00
cpol_cpha				49	50	98.00
	spi_host_speed	111.000s	200000.000us	49	50	98.00
full_cycle				49	50	98.00
	spi_host_speed	111.000s	200000.000us	49	50	98.00
duplex				50	50	100.00
	spi_host_smoke	89.000s	2297.850us	50	50	100.00
tx_rx_only				50	50	100.00
	spi_host_smoke	89.000s	2297.850us	50	50	100.00
stress_all				50	50	100.00
	spi_host_stress_all	214.000s	20399.292us	50	50	100.00
spien				49	50	98.00
	spi_host_spien	312.000s	36501.799us	49	50	98.00
stall				49	50	98.00
	spi_host_status_stall	382.000s	42730.148us	49	50	98.00
Idlecsbactive				50	50	100.00
	spi_host_idlecsbactive	30.000s	5313.513us	50	50	100.00
data_fifo_status				50	50	100.00
	spi_host_overflow_underflow	58.000s	5915.741us	50	50	100.00
alert_test				50	50	100.00
	spi_host_alert_test	2.000s	17.349us	50	50	100.00
intr_test				50	50	100.00
	spi_host_intr_test	2.000s	36.492us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	spi_host_tl_errors	4.000s	599.603us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	spi_host_tl_errors	4.000s	599.603us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	spi_host_csr_hw_reset	2.000s	22.354us	5	5	100.00
	spi_host_csr_rw	2.000s	20.288us	20	20	100.00
	spi_host_csr_aliasing	2.000s	50.626us	5	5	100.00
	spi_host_same_csr_outstanding	2.000s	33.048us	20	20	100.00
tl_d_partial_access				50	50	100.00
	spi_host_csr_hw_reset	2.000s	22.354us	5	5	100.00
	spi_host_csr_rw	2.000s	20.288us	20	20	100.00
	spi_host_csr_aliasing	2.000s	50.626us	5	5	100.00
	spi_host_same_csr_outstanding	2.000s	33.048us	20	20	100.00

V2S

25/25 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	spi_host_tl_intg_err	2.000s	1210.854us	20	20	100.00
	spi_host_sec_cm	2.000s	177.772us	5	5	100.00
sec_cm_bus_integrity				20	20	100.00
	spi_host_tl_intg_err	2.000s	1210.854us	20	20	100.00

unmapped

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				10	10	100.00
	spi_host_upper_range_clkdiv	622.000s	28476.872us	10	10	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	spi_host_speed	115387945816780901280206249051351417012426888762450609328831602822958097095547	145	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (spi_host_scoreboard.sv:220) scoreboard [scoreboard] 'rx_data_q.size' is empty - hence can't compare TXN				1 test run
	spi_host_spien	78364585827276743066712498788516533056994470189843352280537629014566211489152	169	UVM_INFO @ 709896804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed				1 test run
	spi_host_status_stall	113196033907249361080888630206943119049447347793531856768579746779645438734251	6833	UVM_ERROR @ 21456226442 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=21456226000 ps UVM_INFO @ 21456226442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---