Simulation Results: sram_ctrl/ret

 
09/05/2026 02:32:54 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.21 %
  • code
  • 83.42 %
  • assert
  • 96.43 %
  • func
  • 96.80 %
  • block
  • 93.87 %
  • line
  • 95.04 %
  • branch
  • 89.67 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
97.14%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 3.000s 197.989us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 2.000s 38.016us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 33.152us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 3.000s 182.867us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 16.746us 5 5 100.00
csr_mem_rw_with_rand_reset 18 20 90.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 144.607us 18 20 90.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 33.152us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 16.746us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 12.000s 760.902us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 6.000s 170.496us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 18.000s 1279.434us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 180.000s 11940.850us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 8.000s 320.320us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 24.000s 1596.559us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 7.000s 1142.316us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 14.000s 662.544us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 2.000s 48.734us 5 5 100.00
sram_ctrl_partial_access_b2b 318.000s 16942.895us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 2.000s 40.854us 5 5 100.00
sram_ctrl_throughput_w_partial_write 3.000s 55.745us 5 5 100.00
sram_ctrl_throughput_w_readback 2.000s 139.920us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 8.000s 460.241us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 2.000s 54.436us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 52.000s 1623.092us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 12.772us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 127.834us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 127.834us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 38.016us 5 5 100.00
sram_ctrl_csr_rw 2.000s 33.152us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 16.746us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 43.817us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 38.016us 5 5 100.00
sram_ctrl_csr_rw 2.000s 33.152us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 16.746us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 43.817us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 6.000s 5549.612us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_sec_cm 5.000s 935.403us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 2987.557us 20 20 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 935.403us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.000s 2987.557us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 8.000s 460.241us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 8.000s 460.241us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 33.152us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 14.000s 662.544us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 14.000s 662.544us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 14.000s 662.544us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 7.000s 1142.316us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 2.000s 58.362us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 6.000s 5549.612us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 2.000s 387.431us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 3.000s 197.989us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 3.000s 197.989us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 14.000s 662.544us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 935.403us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 7.000s 1142.316us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 935.403us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 935.403us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 3.000s 197.989us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 935.403us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 37.000s 16393.523us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1150) [sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 33916189929483302158577678115657938471923554988262426038576537053157074897288 88
UVM_INFO @ 89948734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 2172339790745481405077842855006943161274710715777939628485078262236801712950 94
UVM_INFO @ 430511717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---