Simulation Results

Simulation Results: ac_range_check

16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
83.32 %

code
93.53 %

assert
97.75 %

func
58.67 %

block
99.10 %

line
99.93 %

branch
98.24 %

toggle
82.43 %

Validation stages

V1		97.89%
V2		97.51%
V2S		100.00%
V3		100.00%
unmapped		100.00%

93/95 passed

97.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
ac_range_check_smoke				19	20	95.00
	ac_range_check_smoke	48.000s	1370.400us	19	20	95.00
ac_range_check_smoke_racl				19	20	95.00
	ac_range_check_smoke_racl	66.000s	9492.144us	19	20	95.00
csr_hw_reset				5	5	100.00
	ac_range_check_csr_hw_reset	3.000s	62.206us	5	5	100.00
csr_rw				20	20	100.00
	ac_range_check_csr_rw	3.000s	195.317us	20	20	100.00
csr_bit_bash				5	5	100.00
	ac_range_check_csr_bit_bash	42.000s	24521.406us	5	5	100.00
csr_aliasing				5	5	100.00
	ac_range_check_csr_aliasing	33.000s	4232.064us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	ac_range_check_csr_mem_rw_with_rand_reset	3.000s	468.995us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	ac_range_check_csr_rw	3.000s	195.317us	20	20	100.00
	ac_range_check_csr_aliasing	33.000s	4232.064us	5	5	100.00

235/241 passed

97.51 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
ac_range_check_lock_range				20	20	100.00
	ac_range_check_lock_range	4.000s	152.507us	20	20	100.00
ac_range_bypass_enable				1	1	100.00
	ac_range_check_bypass	53.000s	508.214us	1	1	100.00
stress_all				44	50	88.00
	ac_range_check_stress_all	310.000s	11755.984us	44	50	88.00
alert_test				50	50	100.00
	ac_range_check_alert_test	29.000s	43.463us	50	50	100.00
intr_test				50	50	100.00
	ac_range_check_intr_test	2.000s	15.935us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	ac_range_check_tl_errors	6.000s	457.675us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	ac_range_check_tl_errors	6.000s	457.675us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	ac_range_check_csr_hw_reset	3.000s	62.206us	5	5	100.00
	ac_range_check_csr_rw	3.000s	195.317us	20	20	100.00
	ac_range_check_csr_aliasing	33.000s	4232.064us	5	5	100.00
	ac_range_check_same_csr_outstanding	7.000s	340.511us	20	20	100.00
tl_d_partial_access				50	50	100.00
	ac_range_check_csr_hw_reset	3.000s	62.206us	5	5	100.00
	ac_range_check_csr_rw	3.000s	195.317us	20	20	100.00
	ac_range_check_csr_aliasing	33.000s	4232.064us	5	5	100.00
	ac_range_check_same_csr_outstanding	7.000s	340.511us	20	20	100.00

V2S

65/65 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	ac_range_check_shadow_reg_errors	20.000s	982.944us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	ac_range_check_shadow_reg_errors	20.000s	982.944us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	ac_range_check_shadow_reg_errors	20.000s	982.944us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	ac_range_check_shadow_reg_errors	20.000s	982.944us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	ac_range_check_shadow_reg_errors_with_csr_rw	130.000s	5454.453us	20	20	100.00
tl_intg_err				25	25	100.00
	ac_range_check_sec_cm	2.000s	17.321us	5	5	100.00
	ac_range_check_tl_intg_err	16.000s	5119.646us	20	20	100.00

50/50 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				50	50	100.00
	ac_range_check_stress_all_with_rand_reset	389.000s	2169.091us	50	50	100.00

unmapped

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				20	20	100.00
	ac_range_check_smoke_high_threshold	49.000s	1051.556us	20	20	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: ac_range_check_reg_block.intr_state				8 test runs
	ac_range_check_smoke	104049645285385163839449380983431397862331021795358465946413323436438112673526	4216	UVM_INFO @ 5177542612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	90306673321616712209791343653789426656894277457829037311431097146358525009100	13427	UVM_INFO @ 1814406305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	28630355202071712104418020720664931553763828359540674106719857356324307278599	14033	UVM_INFO @ 44191619411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_smoke_racl	80853905158298977208576455547176633431962050243184355283244193842815880613367	4390	UVM_INFO @ 13133942940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	10409676447457266955230567540730039777899486060751541293522551337434075890680	4331	UVM_INFO @ 3853186775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	6446295586343362060510567296601890304169960975800603247078021152623149952910	4077	UVM_INFO @ 14109473670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	91955830951866317256770674168668691506797402355926058015110883838324634760162	9752	UVM_INFO @ 3447797104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	32814414882975951431539431014479106769900582881002869819345999977574971635943	4249	UVM_INFO @ 1431483593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---