Simulation Results: aes/gcm_masked

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.06 %
  • code
  • 98.16 %
  • assert
  • 98.57 %
  • func
  • 94.44 %
  • block
  • 98.23 %
  • line
  • 99.42 %
  • branch
  • 95.08 %
  • toggle
  • 98.13 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.85%
V2S
97.89%
V3
10.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 97.898us 1 1 100.00
smoke 50 50 100.00
aes_smoke 6.000s 152.512us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 2.000s 69.544us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 3.000s 154.412us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 9.000s 979.078us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 4.000s 876.368us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 175.904us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 3.000s 154.412us 20 20 100.00
aes_csr_aliasing 4.000s 876.368us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 6.000s 152.512us 50 50 100.00
aes_config_error 14.000s 400.012us 50 50 100.00
aes_stress 17.000s 1075.271us 50 50 100.00
key_length 150 150 100.00
aes_smoke 6.000s 152.512us 50 50 100.00
aes_config_error 14.000s 400.012us 50 50 100.00
aes_stress 17.000s 1075.271us 50 50 100.00
back2back 100 100 100.00
aes_stress 17.000s 1075.271us 50 50 100.00
aes_b2b 32.000s 445.355us 50 50 100.00
backpressure 50 50 100.00
aes_stress 17.000s 1075.271us 50 50 100.00
multi_message 199 200 99.50
aes_smoke 6.000s 152.512us 50 50 100.00
aes_config_error 14.000s 400.012us 50 50 100.00
aes_stress 17.000s 1075.271us 50 50 100.00
aes_alert_reset 12.000s 900.371us 49 50 98.00
failure_test 149 150 99.33
aes_man_cfg_err 5.000s 206.386us 50 50 100.00
aes_config_error 14.000s 400.012us 50 50 100.00
aes_alert_reset 12.000s 900.371us 49 50 98.00
trigger_clear_test 50 50 100.00
aes_clear 18.000s 880.366us 50 50 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 27.000s 1631.559us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 13.000s 700.003us 1 1 100.00
reset_recovery 49 50 98.00
aes_alert_reset 12.000s 900.371us 49 50 98.00
stress 50 50 100.00
aes_stress 17.000s 1075.271us 50 50 100.00
sideload 100 100 100.00
aes_stress 17.000s 1075.271us 50 50 100.00
aes_sideload 29.000s 1602.758us 50 50 100.00
deinitialization 50 50 100.00
aes_deinit 12.000s 611.448us 50 50 100.00
stress_all 10 10 100.00
aes_stress_all 84.000s 3707.273us 10 10 100.00
gcm_save_and_restore 100 100 100.00
aes_gcm_save_restore 8.000s 400.648us 100 100 100.00
alert_test 50 50 100.00
aes_alert_test 7.000s 54.484us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 4.000s 89.472us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 4.000s 89.472us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 2.000s 69.544us 5 5 100.00
aes_csr_rw 3.000s 154.412us 20 20 100.00
aes_csr_aliasing 4.000s 876.368us 5 5 100.00
aes_same_csr_outstanding 3.000s 97.461us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 2.000s 69.544us 5 5 100.00
aes_csr_rw 3.000s 154.412us 20 20 100.00
aes_csr_aliasing 4.000s 876.368us 5 5 100.00
aes_same_csr_outstanding 3.000s 97.461us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 14.000s 630.625us 50 50 100.00
fault_inject 676 700 96.57
aes_fi 21.000s 916.425us 50 50 100.00
aes_control_fi 61.000s 0.000us 286 300 95.33
aes_cipher_fi 61.000s 0.000us 340 350 97.14
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 4.000s 962.144us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 4.000s 962.144us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 4.000s 962.144us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 4.000s 962.144us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 5.000s 352.522us 20 20 100.00
tl_intg_err 25 25 100.00
aes_sec_cm 10.000s 1157.542us 5 5 100.00
aes_tl_intg_err 7.000s 1569.891us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 7.000s 1569.891us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 49 50 98.00
aes_alert_reset 12.000s 900.371us 49 50 98.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 4.000s 962.144us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 4.000s 962.144us 20 20 100.00
sec_cm_main_config_sparse 216 220 98.18
aes_smoke 6.000s 152.512us 50 50 100.00
aes_stress 17.000s 1075.271us 50 50 100.00
aes_alert_reset 12.000s 900.371us 49 50 98.00
aes_core_fi 74.000s 10045.820us 67 70 95.71
sec_cm_gcm_config_sparse 267 270 98.89
aes_gcm_save_restore 8.000s 400.648us 100 100 100.00
aes_config_error 14.000s 400.012us 50 50 100.00
aes_stress 17.000s 1075.271us 50 50 100.00
aes_core_fi 74.000s 10045.820us 67 70 95.71
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 4.000s 962.144us 20 20 100.00
sec_cm_aux_config_regwen 99 100 99.00
aes_readability 7.000s 784.928us 49 50 98.00
aes_stress 17.000s 1075.271us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 17.000s 1075.271us 50 50 100.00
aes_sideload 29.000s 1602.758us 50 50 100.00
sec_cm_key_sw_unreadable 49 50 98.00
aes_readability 7.000s 784.928us 49 50 98.00
sec_cm_data_reg_sw_unreadable 49 50 98.00
aes_readability 7.000s 784.928us 49 50 98.00
sec_cm_key_sec_wipe 49 50 98.00
aes_readability 7.000s 784.928us 49 50 98.00
sec_cm_iv_config_sec_wipe 49 50 98.00
aes_readability 7.000s 784.928us 49 50 98.00
sec_cm_data_reg_sec_wipe 49 50 98.00
aes_readability 7.000s 784.928us 49 50 98.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 17.000s 1075.271us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 17.000s 1075.271us 50 50 100.00
sec_cm_main_fsm_sparse 50 50 100.00
aes_fi 21.000s 916.425us 50 50 100.00
sec_cm_main_fsm_redun 725 750 96.67
aes_fi 21.000s 916.425us 50 50 100.00
aes_control_fi 61.000s 0.000us 286 300 95.33
aes_cipher_fi 61.000s 0.000us 340 350 97.14
aes_ctr_fi 61.000s 0.000us 49 50 98.00
sec_cm_cipher_fsm_sparse 50 50 100.00
aes_fi 21.000s 916.425us 50 50 100.00
sec_cm_cipher_fsm_redun 676 700 96.57
aes_fi 21.000s 916.425us 50 50 100.00
aes_control_fi 61.000s 0.000us 286 300 95.33
aes_cipher_fi 61.000s 0.000us 340 350 97.14
sec_cm_cipher_ctr_redun 340 350 97.14
aes_cipher_fi 61.000s 0.000us 340 350 97.14
sec_cm_ctr_fsm_sparse 50 50 100.00
aes_fi 21.000s 916.425us 50 50 100.00
sec_cm_ctr_fsm_redun 385 400 96.25
aes_fi 21.000s 916.425us 50 50 100.00
aes_control_fi 61.000s 0.000us 286 300 95.33
aes_ctr_fi 61.000s 0.000us 49 50 98.00
sec_cm_ghash_fsm_sparse 50 50 100.00
aes_fi 21.000s 916.425us 50 50 100.00
sec_cm_ctrl_sparse 725 750 96.67
aes_fi 21.000s 916.425us 50 50 100.00
aes_control_fi 61.000s 0.000us 286 300 95.33
aes_cipher_fi 61.000s 0.000us 340 350 97.14
aes_ctr_fi 61.000s 0.000us 49 50 98.00
sec_cm_main_fsm_global_esc 49 50 98.00
aes_alert_reset 12.000s 900.371us 49 50 98.00
sec_cm_main_fsm_local_esc 725 750 96.67
aes_fi 21.000s 916.425us 50 50 100.00
aes_control_fi 61.000s 0.000us 286 300 95.33
aes_cipher_fi 61.000s 0.000us 340 350 97.14
aes_ctr_fi 61.000s 0.000us 49 50 98.00
sec_cm_cipher_fsm_local_esc 725 750 96.67
aes_fi 21.000s 916.425us 50 50 100.00
aes_control_fi 61.000s 0.000us 286 300 95.33
aes_cipher_fi 61.000s 0.000us 340 350 97.14
aes_ctr_fi 61.000s 0.000us 49 50 98.00
sec_cm_ctr_fsm_local_esc 385 400 96.25
aes_fi 21.000s 916.425us 50 50 100.00
aes_control_fi 61.000s 0.000us 286 300 95.33
aes_ctr_fi 61.000s 0.000us 49 50 98.00
sec_cm_ghash_fsm_local_esc 140 140 100.00
aes_ghash_fi 6.000s 298.098us 90 90 100.00
aes_fi 21.000s 916.425us 50 50 100.00
sec_cm_data_reg_local_esc 676 700 96.57
aes_fi 21.000s 916.425us 50 50 100.00
aes_control_fi 61.000s 0.000us 286 300 95.33
aes_cipher_fi 61.000s 0.000us 340 350 97.14
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 10 10.00
aes_stress_all_with_rand_reset 85.000s 3343.632us 1 10 10.00

Error Messages

   Test seed line log context
Job timed out after * minutes 16 test runs
aes_cipher_fi 99698717050650418164527068881935536521983431579345611761137387795012836348193 None
aes_control_fi 17159562150569157727832886228176293170481484941392649594891334708972554643946 None
aes_ctr_fi 13286257260173828022079298410888789127890637737364602745327184205419593082805 None
aes_control_fi 27398332505672028536875981490187652065795680122841920186767566722897770137925 None
aes_control_fi 36044425085590125527702026626461322130581588624949210662027744529564747562658 None
aes_control_fi 18638432883397168436894056232142506895650041303311416493796925477964209353812 None
aes_control_fi 91745886906013935829335984398317234833720316760275828247333694051327815880158 None
aes_control_fi 18534805295791951891384809152484147842819214944013520918663765280942073874330 None
aes_control_fi 67242780727576780867981962324372128418676126399450755768888567047247191913528 None
aes_cipher_fi 103091960939331531885334754680638904379647692866193718113736931419241349818552 None
aes_control_fi 79967280942232535421784046568146367368010659278243528179757530206763734468017 None
aes_control_fi 12399887700765761177391555592178317314153348539995418299282220626539796957755 None
aes_cipher_fi 61147301580973214415630595320543744745815918620958450645730727791389489002958 None
aes_control_fi 19118991659201385267757706735963903598126811119671058261436017650785754629808 None
aes_control_fi 83142224521135515945817176549251922317922300460881736842696462596243421935700 None
aes_control_fi 77785194420601772818724169778955186353511103894699151636897253563776292355031 None
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 7 test runs
aes_cipher_fi 41827662596321668207419956022069487840669266962554242053569274583456032299059 143
UVM_INFO @ 10013523574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 85593089780387459407935406652349127134496684609388259941924882166725376294812 151
UVM_INFO @ 10147018771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 29260697937261128132444126130743543240064701035010227068872070785816874516659 146
UVM_INFO @ 10005404267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 103803604458512771988757939558354875828295375615202886880942605149235215009775 144
UVM_INFO @ 10014078688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 104418205286314760006284182609736202067904734733804377441521110074087426637893 150
UVM_INFO @ 10015183441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 105155749226395696780484284180287838370727328249834122126014499565364486478633 146
UVM_INFO @ 10042744021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 103981727054162367609271835224894815372254139884023014821518560371446485125060 160
UVM_INFO @ 10016905365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
aes_stress_all_with_rand_reset 106762875481603120274102899566117117930155371150064430894382236449102886158669 252
UVM_INFO @ 2886363583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 43294554648405529866015763747742997372426936332328650939031354572595807174649 731
UVM_INFO @ 5142414131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 2592389555616400412359106490637795135606578093098642420354925575604339433874 1012
UVM_INFO @ 3727964222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 2 test runs
aes_stress_all_with_rand_reset 23028211539829859210790762588753888464526700726497569553046177526203453297288 819
UVM_INFO @ 464866048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 56326039971874878439662099828405965725263638660669558307750153599659459428832 168
UVM_INFO @ 100817691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 2 test runs
aes_core_fi 100759729126030639671323578907174012832270368800201561694259758794928179415260 156
UVM_INFO @ 10020585327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 106766993166622481669946782296364586646033461294104847912833812989427022637684 146
UVM_INFO @ 10011609696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 2 test runs
aes_stress_all_with_rand_reset 43411734016807486389377440344720340666469219245186021201050587929179992082421 294
UVM_INFO @ 486921699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 57157785766823436782313549183891573719972911292141091933310621469241536355981 174
UVM_INFO @ 221986670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 2 test runs
aes_control_fi 83267963227557673832469209949169258881096585863566759123973515991886354818545 149
UVM_INFO @ 10007094893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 96961961271388324905099125455606747739869068191232888331185293223090829927765 142
UVM_INFO @ 10010519715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 15997936425812789777425600466670773042682700511291970250142968530722150358611 643
UVM_INFO @ 1283335326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:307) virtual_sequencer [aes_stress_vseq] Expected GCM phase GCM_AAD, got GCM_TEXT 1 test run
aes_stress_all_with_rand_reset 112520951339177463825545932203784841602447354893738885223088190421227961926668 1954
UVM_INFO @ 5998084275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_readability_vseq.sv:66) virtual_sequencer [aes_readability_vseq] ----|Write data reg was Readable |---- 1 test run
aes_readability 32751057863997762962476909660149833441947398864477480646015217499269093607097 138
UVM_INFO @ 12639063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1142): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) 1 test run
aes_alert_reset 9536228471001557521166174121774070159645323330382695347990179309962602872770 3335
UVM_ERROR @ 17550716 ps: (aes_core.sv:1142) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
UVM_INFO @ 17550716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) 1 test run
aes_core_fi 33780223736853278030095571271295649527288263591158158161225912953530827896659 139
UVM_INFO @ 10045820338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---