Simulation Results: aes/gcm_unmasked

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.75 %
  • code
  • 94.33 %
  • assert
  • 97.94 %
  • func
  • 85.98 %
  • block
  • 95.10 %
  • line
  • 96.44 %
  • branch
  • 89.89 %
  • toggle
  • 98.08 %
  • FSM
  • 92.91 %
Validation stages
V1
100.00%
V2
99.83%
V2S
96.76%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 98.766us 1 1 100.00
smoke 50 50 100.00
aes_smoke 3.000s 101.575us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 2.000s 107.729us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 3.000s 162.413us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 6.000s 326.886us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 4.000s 471.172us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 3.000s 79.600us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 3.000s 162.413us 20 20 100.00
aes_csr_aliasing 4.000s 471.172us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 3.000s 101.575us 50 50 100.00
aes_config_error 5.000s 275.881us 50 50 100.00
aes_stress 4.000s 108.993us 50 50 100.00
key_length 150 150 100.00
aes_smoke 3.000s 101.575us 50 50 100.00
aes_config_error 5.000s 275.881us 50 50 100.00
aes_stress 4.000s 108.993us 50 50 100.00
back2back 100 100 100.00
aes_stress 4.000s 108.993us 50 50 100.00
aes_b2b 8.000s 414.882us 50 50 100.00
backpressure 50 50 100.00
aes_stress 4.000s 108.993us 50 50 100.00
multi_message 200 200 100.00
aes_smoke 3.000s 101.575us 50 50 100.00
aes_config_error 5.000s 275.881us 50 50 100.00
aes_stress 4.000s 108.993us 50 50 100.00
aes_alert_reset 4.000s 213.156us 50 50 100.00
failure_test 149 150 99.33
aes_man_cfg_err 3.000s 88.838us 49 50 98.00
aes_config_error 5.000s 275.881us 50 50 100.00
aes_alert_reset 4.000s 213.156us 50 50 100.00
trigger_clear_test 50 50 100.00
aes_clear 8.000s 402.558us 50 50 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 329.463us 1 1 100.00
reset_recovery 50 50 100.00
aes_alert_reset 4.000s 213.156us 50 50 100.00
stress 50 50 100.00
aes_stress 4.000s 108.993us 50 50 100.00
sideload 100 100 100.00
aes_stress 4.000s 108.993us 50 50 100.00
aes_sideload 4.000s 101.739us 50 50 100.00
deinitialization 50 50 100.00
aes_deinit 4.000s 499.397us 50 50 100.00
stress_all 10 10 100.00
aes_stress_all 24.000s 775.563us 10 10 100.00
alert_test 50 50 100.00
aes_alert_test 3.000s 65.134us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 5.000s 2431.840us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 5.000s 2431.840us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 2.000s 107.729us 5 5 100.00
aes_csr_rw 3.000s 162.413us 20 20 100.00
aes_csr_aliasing 4.000s 471.172us 5 5 100.00
aes_same_csr_outstanding 3.000s 170.423us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 2.000s 107.729us 5 5 100.00
aes_csr_rw 3.000s 162.413us 20 20 100.00
aes_csr_aliasing 4.000s 471.172us 5 5 100.00
aes_same_csr_outstanding 3.000s 170.423us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 4.000s 398.851us 50 50 100.00
fault_inject 662 700 94.57
aes_fi 4.000s 75.924us 50 50 100.00
aes_control_fi 61.000s 0.000us 285 300 95.00
aes_cipher_fi 62.029s 0.000us 327 350 93.43
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 3.000s 173.494us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 3.000s 173.494us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 3.000s 173.494us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 3.000s 173.494us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 334.338us 20 20 100.00
tl_intg_err 24 25 96.00
aes_sec_cm 4.000s 425.692us 5 5 100.00
aes_tl_intg_err 4.000s 199.440us 19 20 95.00
sec_cm_bus_integrity 19 20 95.00
aes_tl_intg_err 4.000s 199.440us 19 20 95.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
aes_alert_reset 4.000s 213.156us 50 50 100.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 173.494us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 173.494us 20 20 100.00
sec_cm_main_config_sparse 219 220 99.55
aes_smoke 3.000s 101.575us 50 50 100.00
aes_stress 4.000s 108.993us 50 50 100.00
aes_alert_reset 4.000s 213.156us 50 50 100.00
aes_core_fi 276.000s 10010.071us 69 70 98.57
sec_cm_gcm_config_sparse 169 170 99.41
aes_config_error 5.000s 275.881us 50 50 100.00
aes_stress 4.000s 108.993us 50 50 100.00
aes_core_fi 276.000s 10010.071us 69 70 98.57
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 173.494us 20 20 100.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 3.000s 82.944us 50 50 100.00
aes_stress 4.000s 108.993us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 4.000s 108.993us 50 50 100.00
aes_sideload 4.000s 101.739us 50 50 100.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 3.000s 82.944us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 3.000s 82.944us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 3.000s 82.944us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 3.000s 82.944us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 3.000s 82.944us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 4.000s 108.993us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 4.000s 108.993us 50 50 100.00
sec_cm_main_fsm_sparse 50 50 100.00
aes_fi 4.000s 75.924us 50 50 100.00
sec_cm_main_fsm_redun 712 750 94.93
aes_fi 4.000s 75.924us 50 50 100.00
aes_control_fi 61.000s 0.000us 285 300 95.00
aes_cipher_fi 62.029s 0.000us 327 350 93.43
aes_ctr_fi 3.000s 92.551us 50 50 100.00
sec_cm_cipher_fsm_sparse 50 50 100.00
aes_fi 4.000s 75.924us 50 50 100.00
sec_cm_cipher_fsm_redun 662 700 94.57
aes_fi 4.000s 75.924us 50 50 100.00
aes_control_fi 61.000s 0.000us 285 300 95.00
aes_cipher_fi 62.029s 0.000us 327 350 93.43
sec_cm_cipher_ctr_redun 327 350 93.43
aes_cipher_fi 62.029s 0.000us 327 350 93.43
sec_cm_ctr_fsm_sparse 50 50 100.00
aes_fi 4.000s 75.924us 50 50 100.00
sec_cm_ctr_fsm_redun 385 400 96.25
aes_fi 4.000s 75.924us 50 50 100.00
aes_control_fi 61.000s 0.000us 285 300 95.00
aes_ctr_fi 3.000s 92.551us 50 50 100.00
sec_cm_ghash_fsm_sparse 50 50 100.00
aes_fi 4.000s 75.924us 50 50 100.00
sec_cm_ctrl_sparse 712 750 94.93
aes_fi 4.000s 75.924us 50 50 100.00
aes_control_fi 61.000s 0.000us 285 300 95.00
aes_cipher_fi 62.029s 0.000us 327 350 93.43
aes_ctr_fi 3.000s 92.551us 50 50 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
aes_alert_reset 4.000s 213.156us 50 50 100.00
sec_cm_main_fsm_local_esc 712 750 94.93
aes_fi 4.000s 75.924us 50 50 100.00
aes_control_fi 61.000s 0.000us 285 300 95.00
aes_cipher_fi 62.029s 0.000us 327 350 93.43
aes_ctr_fi 3.000s 92.551us 50 50 100.00
sec_cm_cipher_fsm_local_esc 712 750 94.93
aes_fi 4.000s 75.924us 50 50 100.00
aes_control_fi 61.000s 0.000us 285 300 95.00
aes_cipher_fi 62.029s 0.000us 327 350 93.43
aes_ctr_fi 3.000s 92.551us 50 50 100.00
sec_cm_ctr_fsm_local_esc 385 400 96.25
aes_fi 4.000s 75.924us 50 50 100.00
aes_control_fi 61.000s 0.000us 285 300 95.00
aes_ctr_fi 3.000s 92.551us 50 50 100.00
sec_cm_ghash_fsm_local_esc 50 50 100.00
aes_fi 4.000s 75.924us 50 50 100.00
sec_cm_data_reg_local_esc 662 700 94.57
aes_fi 4.000s 75.924us 50 50 100.00
aes_control_fi 61.000s 0.000us 285 300 95.00
aes_cipher_fi 62.029s 0.000us 327 350 93.43
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 73.000s 6171.567us 0 10 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 21 test runs
aes_control_fi 86119055270477879701031273924549064681663565710787708324690059703250828389697 None
aes_cipher_fi 14694743327167348262284144239218100776305994461820275226195474937678096878601 None
aes_control_fi 90061660790171980002057668239479496910750639706516474048902032936995427593679 None
aes_control_fi 61542300844396599008373546322433427854332944257995123131555020481770608318316 None
aes_cipher_fi 20745541008098647816557006782747571161355719653634439708369445692312809139203 None
aes_cipher_fi 57879554024058285889528046180367855738592861055553341233546969874933488341176 None
aes_control_fi 15101543741642758803731767994869377517937389721750999972056323247037281816050 None
aes_control_fi 1530100843146507219935888972630749783535535454564896755825459203372870992683 None
aes_cipher_fi 15692482983766584802095670012008459368327942515527037956622151663922233612284 None
aes_control_fi 101452978505388164365849325157063781292990874471928968036055369212357332627856 None
aes_cipher_fi 30361661801881906586225147625229486316653103334095872197760255800061263041995 None
aes_control_fi 39661347460028402895608575147316995701402852219588008112667276428263405399336 None
aes_cipher_fi 19301068926816008336578160431685068085298775071286924736195022431817974912664 None
aes_control_fi 39683905418200473105829768119125835619802438422946334392696138651035095155606 None
aes_control_fi 105484681256710788943323928416201356758874775131631503963021970381762828577223 None
aes_control_fi 101821794651343934573910806501873546192941713145286367245294858136550779627393 None
aes_control_fi 59635533238140194347007042833283533026529775165755065912566059430942733135082 None
aes_control_fi 27572585239356533298257521717106975836085975243372763659029959973226640100554 None
aes_cipher_fi 89591022584107213884235317834024785789731327124108731943752327006932011700783 None
aes_cipher_fi 93427811173609289285702992614959191651579365163631298817678306980725936382225 None
aes_control_fi 61018338816551178950524496506243728425986550611026899357698862687206804461460 None
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 15 test runs
aes_cipher_fi 8618051799911102214376719064180088603295308882085048079190926764511850828879 150
UVM_INFO @ 10005961513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 47124121861344553226257953262014825019300354144636779508057193755081667338204 149
UVM_INFO @ 10003119032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 23843784540595963408136928894509508639207175766639330109353316719186589826285 149
UVM_INFO @ 10002428333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 34791056506182018236064827876836060296743124346476629913011438320028912070166 154
UVM_INFO @ 10028026350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 108145966454711803204682214705610026202785940410864432132612899478960295015206 153
UVM_INFO @ 10008762353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 57159732017291351016442377170969520894586149495079231368452178718334414318098 145
UVM_INFO @ 10002598762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 19907418345891491547061763829783710485819575434850981196580389943115667836935 156
UVM_INFO @ 10002601411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 113043197082453459404074145533310479733121029952887561131713632358783484094904 145
UVM_INFO @ 10003669078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 28175024834574799639378952384765187081634782206877882856848246006323597195307 143
UVM_INFO @ 10028304657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 13146882170498190767617123765589512361928453719069354171878532979076666612286 145
UVM_INFO @ 10012772474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 101683905203590704853060613941949282164296938761302845603711666681882933895324 152
UVM_INFO @ 10019487985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 63512650109543783511292862160849790094265038581888907726960324598869789074005 147
UVM_INFO @ 10019342926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 38200308858726613190897752989657906604590093198844462795659425417618576623805 148
UVM_INFO @ 10009073180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 31078351972160863344553207639994135464320211742068131318073557120235733754238 149
UVM_INFO @ 10008403845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 29651128757721903721152554948764711320750958861913055069961966943035310926735 150
UVM_INFO @ 10007660852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 3 test runs
aes_stress_all_with_rand_reset 57606548793130547797166768515252259845194432526957813411052241957066122938274 149
UVM_INFO @ 50816087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 62020256865031322302877241687148236971461574289494911716480885559164634839117 168
UVM_INFO @ 110486155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 45218555038269654461563286012146020742127832617934496842781333530369375834391 734
UVM_INFO @ 1397098344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
aes_stress_all_with_rand_reset 4261440621951479177372819442339353233260764388914630705485291427525048533237 4058
UVM_INFO @ 6171566529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 18746186777685149107034145802242426796066377279111596816866823169323346991499 2363
UVM_INFO @ 1732359526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 20244207930092169505326942064627983260064172263597977686096678591197426334462 658
UVM_INFO @ 754793443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 2 test runs
aes_stress_all_with_rand_reset 80908723192958256738037132147381382388563170490172644992096003141373491854093 643
UVM_INFO @ 686031869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 59134444549045432444151240926853356854200828045937776072380805931024252716141 780
UVM_INFO @ 303344696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 2 test runs
aes_control_fi 34677867195317199745827233142532725740991353332053809903145439393734753486046 154
UVM_INFO @ 10014824429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 5959673285701947951223951067591205746014397116271158404353087765167304515708 154
UVM_INFO @ 10006814388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:307) virtual_sequencer [aes_reseed_vseq] Expected GCM phase GCM_TEXT, got GCM_TAG 1 test run
aes_stress_all_with_rand_reset 41042155596957290246445261997176671120994108709869075321705778987980043763011 2103
UVM_INFO @ 3099485745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 37253203597402402145436329696965183694695764535835023268603054735305215714871 159
UVM_INFO @ 535311144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1028) virtual_sequencer [aes_common_vseq] expect alert:fatal_fault to fire 1 test run
aes_tl_intg_err 23629090734202318838060863742250751040495625335568252172072375242318783008345 116
UVM_INFO @ 37240835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_manual_config_err_vseq.sv:71) virtual_sequencer [aes_manual_config_err_vseq] WAS ABLE TO TRIGGER OPERATION WITH ILLEGAL MODE 1 test run
aes_man_cfg_err 41637454867789737378423021193124901650524989423795932299040383513479659214067 136
UVM_INFO @ 13841744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) 1 test run
aes_core_fi 25418325824283171038930030234207672441580248286615863631266170030883360257218 143
UVM_INFO @ 10010071065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---