Simulation Results: aon_timer

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.51 %
  • code
  • 95.85 %
  • assert
  • 96.67 %
  • func
  • 100.00 %
  • block
  • 99.40 %
  • line
  • 99.49 %
  • branch
  • 99.15 %
  • toggle
  • 88.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
aon_timer_smoke 3.000s 635.680us 5 5 100.00
csr_hw_reset 5 5 100.00
aon_timer_csr_hw_reset 11.000s 704.553us 5 5 100.00
csr_rw 20 20 100.00
aon_timer_csr_rw 3.000s 457.148us 20 20 100.00
csr_bit_bash 5 5 100.00
aon_timer_csr_bit_bash 29.000s 14021.396us 5 5 100.00
csr_aliasing 5 5 100.00
aon_timer_csr_aliasing 21.000s 393.930us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aon_timer_csr_mem_rw_with_rand_reset 3.000s 377.892us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aon_timer_csr_rw 3.000s 457.148us 20 20 100.00
aon_timer_csr_aliasing 21.000s 393.930us 5 5 100.00
mem_walk 5 5 100.00
aon_timer_mem_walk 3.000s 517.362us 5 5 100.00
mem_partial_access 5 5 100.00
aon_timer_mem_partial_access 3.000s 370.534us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
prescaler 15 15 100.00
aon_timer_prescaler 54.000s 21145.729us 15 15 100.00
jump 5 5 100.00
aon_timer_jump 3.000s 672.496us 5 5 100.00
stress_all 15 15 100.00
aon_timer_stress_all 104.000s 148941.056us 15 15 100.00
alert_test 50 50 100.00
aon_timer_alert_test 29.000s 479.165us 50 50 100.00
intr_test 50 50 100.00
aon_timer_intr_test 3.000s 475.235us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aon_timer_tl_errors 5.000s 626.193us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aon_timer_tl_errors 5.000s 626.193us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aon_timer_csr_hw_reset 11.000s 704.553us 5 5 100.00
aon_timer_csr_rw 3.000s 457.148us 20 20 100.00
aon_timer_csr_aliasing 21.000s 393.930us 5 5 100.00
aon_timer_same_csr_outstanding 10.000s 2440.514us 20 20 100.00
tl_d_partial_access 50 50 100.00
aon_timer_csr_hw_reset 11.000s 704.553us 5 5 100.00
aon_timer_csr_rw 3.000s 457.148us 20 20 100.00
aon_timer_csr_aliasing 21.000s 393.930us 5 5 100.00
aon_timer_same_csr_outstanding 10.000s 2440.514us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 23 25 92.00
aon_timer_sec_cm 10.000s 4140.260us 5 5 100.00
aon_timer_tl_intg_err 22.000s 8255.288us 18 20 90.00
sec_cm_bus_integrity 18 20 90.00
aon_timer_tl_intg_err 22.000s 8255.288us 18 20 90.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_threshold 5 5 100.00
aon_timer_smoke_max_thold 3.000s 644.834us 5 5 100.00
min_threshold 5 5 100.00
aon_timer_smoke_min_thold 3.000s 631.208us 5 5 100.00
wkup_count_hi_cdc 5 5 100.00
aon_timer_wkup_count_cdc_hi 11.000s 3398.494us 5 5 100.00
custom_intr 10 10 100.00
aon_timer_custom_intr 4.000s 691.907us 10 10 100.00
alternating_on_off 5 5 100.00
aon_timer_alternating_enable_on_off 36.000s 4143.196us 5 5 100.00
stress_all_with_rand_reset 15 15 100.00
aon_timer_stress_all_with_rand_reset 57.000s 19890.621us 15 15 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1028) virtual_sequencer [aon_timer_common_vseq] expect alert:fatal_fault to fire 2 test runs
aon_timer_tl_intg_err 91393193308406998089124491488818240783447654691177042162267869456274535203049 94
UVM_INFO @ 391619015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aon_timer_tl_intg_err 37469239114076845575740170976512140487103267725015700586179635111323953544487 87
UVM_INFO @ 328016375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---