Simulation Results

Simulation Results: csrng

16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.32 %

code
96.26 %

assert
95.85 %

func
90.86 %

block
98.62 %

line
99.61 %

branch
96.55 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		96.94%
V2S		99.85%
V3		0.00%

105/105 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	csrng_smoke	5.000s	269.183us	50	50	100.00
csr_hw_reset				5	5	100.00
	csrng_csr_hw_reset	33.000s	71.679us	5	5	100.00
csr_rw				20	20	100.00
	csrng_csr_rw	33.000s	24.452us	20	20	100.00
csr_bit_bash				5	5	100.00
	csrng_csr_bit_bash	35.000s	65.878us	5	5	100.00
csr_aliasing				5	5	100.00
	csrng_csr_aliasing	34.000s	49.517us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	csrng_csr_mem_rw_with_rand_reset	34.000s	58.746us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	csrng_csr_rw	33.000s	24.452us	20	20	100.00
	csrng_csr_aliasing	34.000s	49.517us	5	5	100.00

1425/1470 passed

96.94 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	35.000s	92.507us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	59.000s	1163.631us	500	500	100.00
err				500	500	100.00
	csrng_err	33.000s	31.431us	500	500	100.00
cmds				7	50	14.00
	csrng_cmds	110.000s	8149.418us	7	50	14.00
life cycle				7	50	14.00
	csrng_cmds	110.000s	8149.418us	7	50	14.00
stress_all				48	50	96.00
	csrng_stress_all	1271.000s	60735.739us	48	50	96.00
intr_test				50	50	100.00
	csrng_intr_test	33.000s	76.881us	50	50	100.00
alert_test				50	50	100.00
	csrng_alert_test	33.000s	19.174us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	csrng_tl_errors	13.000s	506.038us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	csrng_tl_errors	13.000s	506.038us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	csrng_csr_hw_reset	33.000s	71.679us	5	5	100.00
	csrng_csr_rw	33.000s	24.452us	20	20	100.00
	csrng_csr_aliasing	34.000s	49.517us	5	5	100.00
	csrng_same_csr_outstanding	18.000s	39.511us	20	20	100.00
tl_d_partial_access				50	50	100.00
	csrng_csr_hw_reset	33.000s	71.679us	5	5	100.00
	csrng_csr_rw	33.000s	24.452us	20	20	100.00
	csrng_csr_aliasing	34.000s	49.517us	5	5	100.00
	csrng_same_csr_outstanding	18.000s	39.511us	20	20	100.00

V2S

1343/1345 passed

99.85 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	csrng_sec_cm	14.000s	135.852us	5	5	100.00
	csrng_tl_intg_err	10.000s	215.509us	20	20	100.00
sec_cm_config_regwen				70	70	100.00
	csrng_regwen	33.000s	13.034us	50	50	100.00
	csrng_csr_rw	33.000s	24.452us	20	20	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	59.000s	1163.631us	500	500	100.00
sec_cm_intersig_mubi				48	50	96.00
	csrng_stress_all	1271.000s	60735.739us	48	50	96.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	35.000s	92.507us	200	200	100.00
	csrng_err	33.000s	31.431us	500	500	100.00
	csrng_sec_cm	14.000s	135.852us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	35.000s	92.507us	200	200	100.00
	csrng_err	33.000s	31.431us	500	500	100.00
	csrng_sec_cm	14.000s	135.852us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	35.000s	92.507us	200	200	100.00
	csrng_err	33.000s	31.431us	500	500	100.00
	csrng_sec_cm	14.000s	135.852us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	35.000s	92.507us	200	200	100.00
	csrng_err	33.000s	31.431us	500	500	100.00
	csrng_sec_cm	14.000s	135.852us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	35.000s	92.507us	200	200	100.00
	csrng_err	33.000s	31.431us	500	500	100.00
	csrng_sec_cm	14.000s	135.852us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	59.000s	1163.631us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	35.000s	92.507us	200	200	100.00
	csrng_err	33.000s	31.431us	500	500	100.00
sec_cm_constants_lc_gated				48	50	96.00
	csrng_stress_all	1271.000s	60735.739us	48	50	96.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	59.000s	1163.631us	500	500	100.00
sec_cm_tile_link_bus_integrity				20	20	100.00
	csrng_tl_intg_err	10.000s	215.509us	20	20	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	35.000s	92.507us	200	200	100.00
	csrng_err	33.000s	31.431us	500	500	100.00
	csrng_sec_cm	14.000s	135.852us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	35.000s	92.507us	200	200	100.00
	csrng_err	33.000s	31.431us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	35.000s	92.507us	200	200	100.00
	csrng_err	33.000s	31.431us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	35.000s	92.507us	200	200	100.00
	csrng_err	33.000s	31.431us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	35.000s	92.507us	200	200	100.00
	csrng_err	33.000s	31.431us	500	500	100.00
	csrng_sec_cm	14.000s	135.852us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	35.000s	92.507us	200	200	100.00
	csrng_err	33.000s	31.431us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	10801.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])				41 test runs
	csrng_cmds	53150193214737664679413900469689263918600438224911375682512354489016483941941	130	UVM_INFO @ 149006791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	42893199134189947512441374651394274066051066407399008268607969910770737512829	130	UVM_INFO @ 55990896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	105889916489004510698926717835890195951961221743999182554215958049112572419733	140	UVM_INFO @ 165198761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	9775161961820052102312570450413636049501510471996335744458646930733347035905	130	UVM_INFO @ 339499469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	13400603582129294652427485165528116105291801282086740244231262113580459275959	130	UVM_INFO @ 76210225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	100533046997661275641550117246304269353642505128570272203525963696997397122651	130	UVM_INFO @ 40811165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	10944060933412865934717510097559805253978642724598733594545600487459251069087	130	UVM_INFO @ 208566766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	41627235981524595981486082037258127294095435834032639840123249266140854902058	130	UVM_INFO @ 242090132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	11495909972019543304454165124240563388522027950045455112425152390034664494662	130	UVM_INFO @ 487787857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	79140010096145382257807805874043750602602762118312242088076417658664813885700	130	UVM_INFO @ 85179117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	19615614948540466437601238747494400750551496094881271878456578616262315452185	130	UVM_INFO @ 663590216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	52449934814094740731333722391054231108244902060807959759695274456621837002169	130	UVM_INFO @ 21820859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	6667269471007837815681099067208280932851293461183289196605780429650754803040	130	UVM_INFO @ 200149698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	114656442210100783960141020883500154866869676563901971640376278521783912681492	130	UVM_INFO @ 66491651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	44678118969058036853899394080857923064865620803157170045125723381442157090517	130	UVM_INFO @ 193801719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	4692981252350548177342719163217366906370379742982496254704289804387211129940	130	UVM_INFO @ 173692488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	48400115663684457143519763157088082109497487583666337382086394680252309120942	130	UVM_INFO @ 92020448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	114381021986128110404939478787754434656647298055533172617537347983439985214229	130	UVM_INFO @ 16986638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	41797203866268803391351659523058901169197805094472909498014086004362402333633	140	UVM_INFO @ 183914647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	792751923846707743728711195367512748771296162999070477139576467797113720795	139	UVM_INFO @ 75347898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	90990507669073994686122681965254391446625740664857213454722718349543475108958	130	UVM_INFO @ 51761054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	36690907007078582615967302030891750934549847156351516737521019677961460128879	130	UVM_INFO @ 36713756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	51408613140535059040161864420478638197965207824941111846927491723425115484117	130	UVM_INFO @ 16027001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	76498943370864614028605328749111358658365910063397769213155215934171013495865	130	UVM_INFO @ 81979320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	56307104304869345848905365494285087870247849003692083724398971305680004987508	140	UVM_INFO @ 498419818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	51556492765434500955149816033560010994460563818997591159193481285445325484850	140	UVM_INFO @ 80044357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	94590007437421233556122432934301329103907547574697690256947217774535506520899	130	UVM_INFO @ 22737609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	40386090891594703294976161818971455005423412879362705683700764286270261533009	150	UVM_INFO @ 126643870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	4205398208591028329756100354525352136966384216148019085344422812241997703267	130	UVM_INFO @ 6710292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	94466359229443746533770276574280576601535130278372307112803320434192837162884	130	UVM_INFO @ 317230619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	82472771068368688810096199581349108031955989313416580599172853330782116243459	140	UVM_INFO @ 1042625567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	67280462681368245526590603252736511788209685966399227292521232195285852126365	130	UVM_INFO @ 785427016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	74916529393483513790250568577458078144275453492323065764360151571431945632301	130	UVM_INFO @ 475419434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	75701782157057267355675002101137728552323417826651379456655857438048886670462	130	UVM_INFO @ 127167520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	61392576478791095852087089307279970447208691319709229872449833033300370377483	140	UVM_INFO @ 36587062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	22355684173440791252996039252210409011713028256504470233650648301415771483647	130	UVM_INFO @ 333747259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	7333288320713878855104647978676669493143474036953857159685988480529531195095	130	UVM_INFO @ 564368038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	37683533350524447946469801165488846732218554751706202592231275988552746888814	130	UVM_INFO @ 68592218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	88407408321773830607708623329078031988356072102239700095715946940156191746286	130	UVM_INFO @ 145994550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	46937980864282544942099536838679058038092972254514663098322474897840730303355	130	UVM_INFO @ 32622910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	42649948318080349631223508418588511719480776420804168540553505100674338168891	130	UVM_INFO @ 971054354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				10 test runs
	csrng_stress_all_with_rand_reset	60374544681779803343112563614254459710236816938911774723616196063842299444521	None
	csrng_stress_all_with_rand_reset	62616962259083754513248546057493384814553517425359427556750935450975784835731	None
	csrng_stress_all_with_rand_reset	92382659789237990447220769105150554162257369800233775511730971604675736421557	None
	csrng_stress_all_with_rand_reset	66168168645759550946902553108275644220260076543805226965781667760137523809783	None
	csrng_stress_all_with_rand_reset	91360836695897879603604357660688005056005558061046292091747592483403601023657	None
	csrng_stress_all_with_rand_reset	62435794904977651164483706658758064310620130392251624027431317328137226731292	None
	csrng_stress_all_with_rand_reset	48321724401844070713094410619772657122085402284465212481521762739416063052723	None
	csrng_stress_all_with_rand_reset	89415757862430420927059334301304547126907385810122430231507681118402243377622	None
	csrng_stress_all_with_rand_reset	58134219748361833982266787656310086528920607223364152047418652635244310467025	None
	csrng_stress_all_with_rand_reset	35044819519656046467380692475552281374530812821161316473195111638957968240680	None
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq				2 test runs
	csrng_stress_all	62967309237618025503145799045659301319062465025475866418880513694678285880900	139	UVM_INFO @ 56990660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	67143859651304749978132495917722198387433808409292453623225935667818530466736	142	UVM_INFO @ 54944465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:629) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [] vs [*])				2 test runs
	csrng_cmds	67212368503557260814771643411610924079292899037515501651606516723228013769601	139	UVM_INFO @ 79347804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	91628580632454839594157340849335721325356973166247576634896143406632299880488	149	UVM_INFO @ 75869752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---