Simulation Results: dma

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.31 %
  • code
  • 92.23 %
  • assert
  • 95.97 %
  • func
  • 76.73 %
  • block
  • 97.43 %
  • line
  • 96.94 %
  • branch
  • 95.90 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 9.000s 341.047us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 10.000s 4445.509us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 9.000s 1322.093us 50 50 100.00
csr_hw_reset 5 5 100.00
dma_csr_hw_reset 2.000s 60.640us 5 5 100.00
csr_rw 20 20 100.00
dma_csr_rw 2.000s 21.569us 20 20 100.00
csr_bit_bash 5 5 100.00
dma_csr_bit_bash 15.000s 3082.672us 5 5 100.00
csr_aliasing 5 5 100.00
dma_csr_aliasing 7.000s 2486.023us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 55.992us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
dma_csr_rw 2.000s 21.569us 20 20 100.00
dma_csr_aliasing 7.000s 2486.023us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 129.000s 13687.019us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 521.000s 74105.905us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 692.000s 107454.633us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 692.000s 107454.633us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 521.000s 74105.905us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 1629.000s 213876.768us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 692.000s 107454.633us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 12.000s 2915.592us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 316.000s 25577.893us 3 3 100.00
alert_test 50 50 100.00
dma_alert_test 2.000s 54.188us 50 50 100.00
intr_test 50 50 100.00
dma_intr_test 2.000s 26.721us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
dma_tl_errors 4.000s 182.794us 20 20 100.00
tl_d_illegal_access 20 20 100.00
dma_tl_errors 4.000s 182.794us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
dma_csr_hw_reset 2.000s 60.640us 5 5 100.00
dma_csr_rw 2.000s 21.569us 20 20 100.00
dma_csr_aliasing 7.000s 2486.023us 5 5 100.00
dma_same_csr_outstanding 3.000s 230.694us 20 20 100.00
tl_d_partial_access 50 50 100.00
dma_csr_hw_reset 2.000s 60.640us 5 5 100.00
dma_csr_rw 2.000s 21.569us 20 20 100.00
dma_csr_aliasing 7.000s 2486.023us 5 5 100.00
dma_same_csr_outstanding 3.000s 230.694us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 25.000s 1170.770us 5 5 100.00
dma_generic_stress 1629.000s 213876.768us 5 5 100.00
dma_handshake_stress 692.000s 107454.633us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 13.000s 332.091us 15 15 100.00
tl_intg_err 25 25 100.00
dma_tl_intg_err 5.000s 95.536us 20 20 100.00
dma_sec_cm 2.000s 52.460us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 184.000s 32796.608us 25 25 100.00
dma_longer_transfer 8.000s 2194.846us 5 5 100.00
dma_stress_all_with_rand_reset 27.000s 1055.329us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 1901531322204274710793749159141120406844774933791257916953684814181343849984 141
UVM_INFO @ 1055329338ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---