Simulation Results: edn/edn0

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.86 %
  • code
  • 95.28 %
  • assert
  • 97.57 %
  • func
  • 58.74 %
  • block
  • 96.95 %
  • line
  • 98.68 %
  • branch
  • 93.23 %
  • toggle
  • 89.22 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.38%
V2S
100.00%
V3
88.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 2.000s 43.923us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 2.000s 19.522us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 2.000s 23.657us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 7.000s 508.810us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 3.000s 34.188us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 4.000s 35.738us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 2.000s 23.657us 20 20 100.00
edn_csr_aliasing 3.000s 34.188us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 80.000s 9147.688us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 80.000s 9147.688us 300 300 100.00
genbits 300 300 100.00
edn_genbits 80.000s 9147.688us 300 300 100.00
interrupts 50 50 100.00
edn_intr 2.000s 21.103us 50 50 100.00
alerts 200 200 100.00
edn_alert 3.000s 32.420us 200 200 100.00
errs 100 100 100.00
edn_err 3.000s 34.637us 100 100 100.00
disable 94 100 94.00
edn_disable 2.000s 29.701us 50 50 100.00
edn_disable_auto_req_mode 5.000s 500.000us 44 50 88.00
stress_all 50 50 100.00
edn_stress_all 8.000s 704.957us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 2.000s 21.014us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 3.000s 101.045us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 4.000s 38.267us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 4.000s 38.267us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 2.000s 19.522us 5 5 100.00
edn_csr_rw 2.000s 23.657us 20 20 100.00
edn_csr_aliasing 3.000s 34.188us 5 5 100.00
edn_same_csr_outstanding 3.000s 246.092us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 2.000s 19.522us 5 5 100.00
edn_csr_rw 2.000s 23.657us 20 20 100.00
edn_csr_aliasing 3.000s 34.188us 5 5 100.00
edn_same_csr_outstanding 3.000s 246.092us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 8.000s 4438.522us 5 5 100.00
edn_tl_intg_err 4.000s 405.877us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 2.000s 57.795us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 3.000s 32.420us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 8.000s 4438.522us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 8.000s 4438.522us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 8.000s 4438.522us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 8.000s 4438.522us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 3.000s 32.420us 200 200 100.00
edn_sec_cm 8.000s 4438.522us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 3.000s 32.420us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 4.000s 405.877us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 44 50 88.00
edn_stress_all_with_rand_reset 145.000s 11378.944us 44 50 88.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
edn_stress_all_with_rand_reset 88994612974269309998988269598528922428258169246480620050538902693689937739713 173
UVM_INFO @ 342735021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 112685553517984637500170467220054055967220039245229269730142221229512700128764 162
UVM_INFO @ 1904873747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 69712265840791942936466252605160380312867800976282435487756013417910037677661 179
UVM_INFO @ 752006840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 72577568380739990991534004879498318011303289159798061451619905497072229689596 162
UVM_INFO @ 1055945329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 16485159188959550863083381496386107442500243758604424865029140872398231283324 162
UVM_INFO @ 920432202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 52990974129688015442166601072143133173289168949102819489568862925561214191111 183
UVM_INFO @ 1506586389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
edn_disable_auto_req_mode 19102584877571764907020659669658095285880312558332375013527366844119384673466 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 79908767416960049494034200579655773985466110558222573454063978551557666698529 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 92042120980954089820603368650699173027246978105150093632374504735073437655877 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 80781627931232486291042641001701637439915761734963785911422968102371328888724 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:431) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 2 test runs
edn_disable_auto_req_mode 82413936635677362692176436141780008274961792834934583831503147468797878203008 103
UVM_INFO @ 35471898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 11179173321311353706456677138688522607806390158747813987183319966135354014840 103
UVM_INFO @ 42482284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---