Simulation Results: edn/edn1

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.10 %
  • code
  • 95.93 %
  • assert
  • 97.14 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.00 %
  • toggle
  • 96.15 %
  • FSM
  • 95.45 %
Validation stages
V1
99.05%
V2
99.28%
V2S
100.00%
V3
88.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.180s 18.932us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.060s 18.302us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.150s 14.414us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.320s 503.628us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.590s 34.393us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
edn_csr_mem_rw_with_rand_reset 90.570s 10016.425us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.150s 14.414us 20 20 100.00
edn_csr_aliasing 1.590s 34.393us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 4.760s 761.521us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 4.760s 761.521us 300 300 100.00
genbits 300 300 100.00
edn_genbits 4.760s 761.521us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.180s 21.496us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.660s 34.822us 200 200 100.00
errs 100 100 100.00
edn_err 1.310s 59.816us 100 100 100.00
disable 93 100 93.00
edn_disable 1.020s 22.545us 50 50 100.00
edn_disable_auto_req_mode 4.710s 500.000us 43 50 86.00
stress_all 50 50 100.00
edn_stress_all 6.190s 720.768us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.130s 14.076us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.190s 205.142us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.230s 564.861us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.230s 564.861us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.060s 18.302us 5 5 100.00
edn_csr_rw 1.150s 14.414us 20 20 100.00
edn_csr_aliasing 1.590s 34.393us 5 5 100.00
edn_same_csr_outstanding 1.490s 63.114us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.060s 18.302us 5 5 100.00
edn_csr_rw 1.150s 14.414us 20 20 100.00
edn_csr_aliasing 1.590s 34.393us 5 5 100.00
edn_same_csr_outstanding 1.490s 63.114us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 4.150s 306.650us 5 5 100.00
edn_tl_intg_err 2.900s 216.472us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.010s 48.861us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.660s 34.822us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.150s 306.650us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.150s 306.650us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.150s 306.650us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.150s 306.650us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.660s 34.822us 200 200 100.00
edn_sec_cm 4.150s 306.650us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.660s 34.822us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.900s 216.472us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 44 50 88.00
edn_stress_all_with_rand_reset 126.080s 11674.817us 44 50 88.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
edn_disable_auto_req_mode 100167837095314095120006824797967513122181135189382245719644706640448142723321 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 74082873852465122520878122209354295261273310975747154826655353951388284078036 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 40069300358278988502315637006718802195800909616129364001815624476540631990939 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 106474177715077576955117270119982404363527418996509328154145759717987654725080 90
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 45391097593367071390780598984836498464697998719612679612245051329408238768670 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
edn_stress_all_with_rand_reset 28073843793954706888495034666889894034761180111857794184150367222120402137944 125
UVM_INFO @ 1062065814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 96222171813490744348388286886138817290554180311487764844467588215374647291868 168
UVM_INFO @ 959614597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 80863478140870394951775727719260958906284683567691031251754158052953406123864 294
UVM_INFO @ 1196852171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 70800628149547802761540130382919152418707575256027241812669742003767280461842 213
UVM_INFO @ 1671178089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit 2 test runs
edn_stress_all_with_rand_reset 38791673186506754595762757011261491055906719376593807768707583896823010364298 231
/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 1064085562 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup
edn_stress_all_with_rand_reset 108081784131758377580295090603431027381639761189646178171692891567488043085715 195
/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 1107508435 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 2 test runs
edn_disable_auto_req_mode 57221762246415243640640889635219264763893911149791274266797804940009435128674 88
UVM_INFO @ 30916731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 62398052255127180122247110792890577369949673401034234469160355985585280606088 88
UVM_INFO @ 71101198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [edn_common_vseq] wait timeout occurred! 1 test run
edn_csr_mem_rw_with_rand_reset 49458889064108411847238835524743833063579039360094460765813576915932238386892 89
UVM_INFO @ 10016424843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---