Simulation Results: gpio

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.49 %
  • code
  • 92.63 %
  • assert
  • 96.84 %
  • func
  • 100.00 %
  • line
  • 99.89 %
  • branch
  • 98.38 %
  • cond
  • 95.68 %
  • toggle
  • 94.19 %
  • FSM
  • 75.00 %
Validation stages
V1
100.00%
V2
92.39%
V2S
92.00%
V3
39.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 200 200 100.00
gpio_smoke 2.270s 46.381us 50 50 100.00
gpio_smoke_no_pullup_pulldown 2.200s 206.756us 50 50 100.00
gpio_smoke_en_cdc_prim 2.280s 269.135us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 2.020s 717.773us 50 50 100.00
csr_hw_reset 5 5 100.00
gpio_csr_hw_reset 1.020s 19.845us 5 5 100.00
csr_rw 20 20 100.00
gpio_csr_rw 1.100s 32.215us 20 20 100.00
csr_bit_bash 5 5 100.00
gpio_csr_bit_bash 6.820s 144.143us 5 5 100.00
csr_aliasing 5 5 100.00
gpio_csr_aliasing 2.910s 57.631us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
gpio_csr_mem_rw_with_rand_reset 2.180s 34.347us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
gpio_csr_rw 1.100s 32.215us 20 20 100.00
gpio_csr_aliasing 2.910s 57.631us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 100 100 100.00
gpio_random_dout_din 1.880s 122.773us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 2.110s 60.340us 50 50 100.00
out_in_regs_read_write 50 50 100.00
gpio_dout_din_regs_random_rw 1.430s 248.575us 50 50 100.00
gpio_interrupt_programming 50 50 100.00
gpio_intr_rand_pgm 2.060s 53.003us 50 50 100.00
random_interrupt_trigger 50 50 100.00
gpio_rand_intr_trigger 5.090s 243.268us 50 50 100.00
interrupt_and_noise_filter 50 50 100.00
gpio_intr_with_filter_rand_intr_event 5.690s 92.691us 50 50 100.00
noise_filter_stress 50 50 100.00
gpio_filter_stress 23.020s 344.458us 50 50 100.00
regs_long_reads_and_writes 50 50 100.00
gpio_random_long_reg_writes_reg_reads 6.690s 384.659us 50 50 100.00
full_random 50 50 100.00
gpio_full_random 1.550s 93.038us 50 50 100.00
stress_all 5 50 10.00
gpio_stress_all 173.930s 70424.977us 5 50 10.00
alert_test 50 50 100.00
gpio_alert_test 0.920s 19.369us 50 50 100.00
intr_test 50 50 100.00
gpio_intr_test 0.960s 16.114us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
gpio_tl_errors 3.800s 182.433us 20 20 100.00
tl_d_illegal_access 20 20 100.00
gpio_tl_errors 3.800s 182.433us 20 20 100.00
tl_d_outstanding_access 44 50 88.00
gpio_csr_rw 1.100s 32.215us 20 20 100.00
gpio_same_csr_outstanding 1.560s 122.716us 14 20 70.00
gpio_csr_aliasing 2.910s 57.631us 5 5 100.00
gpio_csr_hw_reset 1.020s 19.845us 5 5 100.00
tl_d_partial_access 44 50 88.00
gpio_csr_rw 1.100s 32.215us 20 20 100.00
gpio_same_csr_outstanding 1.560s 122.716us 14 20 70.00
gpio_csr_aliasing 2.910s 57.631us 5 5 100.00
gpio_csr_hw_reset 1.020s 19.845us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 23 25 92.00
gpio_tl_intg_err 3.440s 748.322us 18 20 90.00
gpio_sec_cm 1.280s 136.075us 5 5 100.00
sec_cm_bus_integrity 18 20 90.00
gpio_tl_intg_err 3.440s 748.322us 18 20 90.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 39 50 78.00
gpio_rand_straps 0.940s 14.155us 39 50 78.00
stress_all_with_rand_reset 0 50 0.00
gpio_stress_all_with_rand_reset 25.570s 4102.320us 0 50 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 50 50 100.00
gpio_inp_prd_cnt 0.950s 21.985us 50 50 100.00

Error Messages

   Test seed line log context
UVM_ERROR (gpio_scoreboard.sv:248) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 56 test runs
gpio_stress_all 93415837865541536994448312022947554986601298254658888152816469018954764971475 680
UVM_INFO @ 1736120140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 107891732212531664413700374293763935869629516691313343411966283488538706352887 75
UVM_INFO @ 37689744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 53886674642924623449786303263880835264805712684426655826008169761388053536385 129
UVM_INFO @ 596331244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 81131851028222039797155198409733297027282975421134314648960080980677284616863 414
UVM_INFO @ 885071008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 72550103530144461549580262217504216369769166426595326833302187177466651206312 1218
UVM_INFO @ 6259229658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 78090965821526173202343217128899684382100380291410759660091558391348644768732 152
UVM_INFO @ 1299431311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 81134377220354551747148105003755082334719189443546430754390562077648782636709 364
UVM_INFO @ 1882424628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 83511160262976034300176778944492578122774215580567052388243393031723259003604 669
UVM_INFO @ 4575694729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 110861907396854076813673605926869513606341138154415930494342399975029514406450 514
UVM_INFO @ 7043824418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 28986188879563101768308518845182116256063111416068451363134731373792225424034 930
UVM_INFO @ 18931204365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 35558570823041353989909826312178529287614208741121710207681184333016842118381 75
UVM_INFO @ 2266989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 50944670474545907468444318601847118142374820557570280499654503129293575122504 76
UVM_INFO @ 10035647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 21001303863795883885673512403969601925663151128050458238563260243426093878671 3570
UVM_INFO @ 11543805266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 52242429386588892721371161020822043748663812619821256007291122741150911172072 143
UVM_INFO @ 1128138642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 83903322939123242838994718903701915205827197318288891567626889575811243269724 77
UVM_INFO @ 24443981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 27759816601092730819458775478021116158582606684894671532916635216660048979 441
UVM_INFO @ 1409682877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 11007243412329021393663164291000650498234722564537486041417929772737263696635 349
UVM_INFO @ 1657508945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 83158198789467774174447769909626274263298288644342041592274051612547218776064 325
UVM_INFO @ 2058196613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 112222825830182328866998259632853661128537909617463334226448277007063052734038 724
UVM_INFO @ 7148501389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 75158598178101017651684081383767678696159436243455603434105452956887762899529 1209
UVM_INFO @ 11001027034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 11242691468679542161839632311938922301101831607640026017131544237139968331431 523
UVM_INFO @ 2040105030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 65351478147100035027992468325836457468006054292605050897173110070105799737865 414
UVM_INFO @ 1524533208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 69549567130155227143681345211810828982026256412298538748530536847242518975815 1630
UVM_INFO @ 3902174888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 66724120393125161343917153538372065440054677622154763221621654336236826141757 75
UVM_INFO @ 4724330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 108683274460706142151163256601282289115673795109510643975444777566222806258216 75
UVM_INFO @ 14043308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 91763217163342144554541161162969441547796753655725736073047535629911317817404 79
UVM_INFO @ 776239593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 96774031210059194467513550563970394464935561576914186471976459680907423738706 75
UVM_INFO @ 5744210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 79095650060695458288927309844110560453713874532490470463211384383025099272812 700
UVM_INFO @ 2619690661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 26225488281671036847344579815213355293793526121054449476938269261762289485391 75
UVM_INFO @ 1398706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 80428270547646971618311614226088792731030745788758576374201419067313459588328 605
UVM_INFO @ 6133503980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 19838240156643608497415922226899021736188670392999955678324882419378534266984 75
UVM_INFO @ 4464112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 58650342491055254330162248699581069718699644685896964729731140609286590040916 172
UVM_INFO @ 202857311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 37537072287176407061351010657964219567292337488270286633097912453929904707715 526
UVM_INFO @ 9026299378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 73445266145113604117119264892792499982075199306047916121391582025046328885690 1519
UVM_INFO @ 11253374172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 97239333557499389621806981824005664474754432834074100812490983219654198372590 539
UVM_INFO @ 1973090188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 91479620562516560274091925836315823074792730149545405698140374178366966562503 75
UVM_INFO @ 5771222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 36311881612834878237409060741496457327440569244415821023057121954650248742859 202
UVM_INFO @ 685444970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 20967663730640324859003413078543421068353530634436418200116295247007053774741 2276
UVM_INFO @ 14949918622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 83218530166320294182682816806594821182852314860029828938229389335253047207201 75
UVM_INFO @ 5643379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 65150414354284464909542458373103956911224524820564017130135433238545886831829 203
UVM_INFO @ 1019789826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 60556752141907084878656120239988739888964635422638458783514017339566805629073 75
UVM_INFO @ 1227829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 102944492308284750903701945027300295659131076687365693289352299603509217900133 496
UVM_INFO @ 474240244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 36914685133537483321091669007268291231975430609264437607169611511925449214075 80
UVM_INFO @ 377353175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 113498361756516970536114675264172341314395478659729043781185058620929405712415 359
UVM_INFO @ 2391915614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 53771368639500467169309037553003093795835659346326582845167365977246486997206 1019
UVM_INFO @ 6799513664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 28058120230904280778384788967675991122156865198587742842815000306764786461642 756
UVM_INFO @ 3125980499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 58730475376610832419230475072954213826671173903994760070303091243025958801755 2422
UVM_INFO @ 5981891454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 19272024456648950942363917047055841301746713202855694026027566116323367432124 75
UVM_INFO @ 1084480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 26248498934293364121972812678768121751362088029727312948678318907990270658236 496
UVM_INFO @ 1906536464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 70723160676449217490481272110074122018760948996298979250567585213839646877753 75
UVM_INFO @ 1341507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 71575709934394162064743776738712184525740823470635505876057510921346781882459 127
UVM_INFO @ 658165595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 104515547915956252785942282572586020274141510578939063219417626477542860054839 976
UVM_INFO @ 2635455295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 108506781041745182130635780593044215198408003640631827297684310271263597685215 77
UVM_INFO @ 202928073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 100093688710346840343277110197057978223449677564133651397042450962725698655904 648
UVM_INFO @ 6639302052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 54062050418153504614398826786484833432982774574831838422694208347172704534956 961
UVM_INFO @ 15174199420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 27438989594398463597418611149564902791009484444145856457905996758624561288696 675
UVM_INFO @ 1101430671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [gpio_common_vseq] Check failed (vseq_done) 28 test runs
gpio_stress_all_with_rand_reset 27307207056028757856076880908387837270292201140786422551291862653865986238110 84
UVM_INFO @ 4050767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 83020723860390015433666143973817987206595034505655432693106082546804013530429 80
UVM_INFO @ 138008201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 74257906742449484072980204373589882716022450466822878797517549372598511460167 82
UVM_INFO @ 132476593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 58978155042803101830253009679095231128109790408876902124378759618294619636814 80
UVM_INFO @ 38058612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 43186064568081742704135003145770476538826787048937573940324284442488704530699 89
UVM_INFO @ 416403255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 24792384311465723539823087782057331900284500791616069481391346688143061830783 301
UVM_INFO @ 1447740692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 68773652483383893078249763108383307118577276159262723014353133297797684888695 105
UVM_INFO @ 553004982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 25957204756340048260788467286581737368292684680349882917153318201846289352511 80
UVM_INFO @ 20808947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 106470062362019369553328602531906967556019747414759746766928357166089182960903 82
UVM_INFO @ 13099175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 31825534187418398816427453134670636600508463699790779525277076552126847201237 82
UVM_INFO @ 625749934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 60561095295350652354957893951763278886956358793191387551647463057506630947743 82
UVM_INFO @ 788870746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 112477321910014047340354627967523380323542628425159975711787404536145847869502 80
UVM_INFO @ 3642951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 6921252974914688017463979873086214655518380463282062006892517318089176586136 329
UVM_INFO @ 1072483565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 58611120445419583150842631167337193700782867469616313826915925215822668022590 80
UVM_INFO @ 11803437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 31707597257992553397421146441009707249534882689173668322044551750559151785856 80
UVM_INFO @ 17484294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 67318883654056956622929251187100753862501925805468735000274881543806902918333 247
UVM_INFO @ 544628649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 30320782770954016097840863969222252040394464322680055653378266562056771825858 318
UVM_INFO @ 1668714161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 85481833444309653661202777325719664830624460855328058418001049458498912737979 80
UVM_INFO @ 10379897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 39154524109131478649331001992409860270664004592242481315281834170089263466644 80
UVM_INFO @ 32713717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 3282520212248578131296983422059738330111007465808189122638719042075319011619 81
UVM_INFO @ 659324598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 28503861138780276035148499504614411737378315410743142382115135489034142303491 80
UVM_INFO @ 65298691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 98858412649725288984554651172472273093659422352591957533311990730916184604519 80
UVM_INFO @ 7427421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 19768166711959569866044371398334078756374565095750942815285541406753298435062 80
UVM_INFO @ 103662644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 13945818558441464481842582667257890294081516710242056885839666519456032285007 83
UVM_INFO @ 1585273486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 36354762118164295390825414727513648840985041125649070634896743986510038578476 80
UVM_INFO @ 22573437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 101653501506845184068235088299624120380311428001080725105157353656424747364386 80
UVM_INFO @ 3989779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 91505078927766651623910684357854523232985202941246826591044384084744402174272 80
UVM_INFO @ 21112034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 24438379780066389414356205096886919162584816580925991912978151213579576726857 82
UVM_INFO @ 641372629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 22 test runs
gpio_stress_all_with_rand_reset 10459905451484754676567920381819629889104367755501936436778500031883255058565 282
UVM_INFO @ 481226999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 84799416673171797095315273213649096630314187450891616733617795136707637796546 78
UVM_INFO @ 26971361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 91845083930905203375907230097440934704190696559357153106454147128649818170464 80
UVM_INFO @ 8389170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 90880294364513270459709221269022227340741753506231810774204831753964990779516 319
UVM_INFO @ 1321585650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 108052256966426717285010503135507090256607345513302746816662387935861519433749 78
UVM_INFO @ 27672596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 88597194935067696536847852038331197131950963179858019983984343976096951077108 78
UVM_INFO @ 3098734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 115360991858799124985467848803308950253049559494937537609013124904786458689466 273
UVM_INFO @ 4102320220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 60347989335093095008490974399898526454815540272166525239405206999704787163555 386
UVM_INFO @ 1560138646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 11396918783914057075433515869408551982951537427301882056834210284923497925233 78
UVM_INFO @ 4648870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 29670395933962214411173499831169402719481808756696574254969738142566334629279 237
UVM_INFO @ 1217340069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 16968822772349590672964926872935984126892225771371031811972819444384318705752 475
UVM_INFO @ 1810379015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 109093259512833749348789198740127853086141832603623216172103324000730810703059 206
UVM_INFO @ 1671364169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 28148384346001519331654826923717247833108285391997953753113443361482245826858 78
UVM_INFO @ 255973715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 76295584961763336304151519309086379864604443232964017794359596134835652274415 78
UVM_INFO @ 392811527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 71040655171101407610030194466236121462845120544091882289680086309420365588121 78
UVM_INFO @ 1046246279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 111596383375641873986439027193153947604307001573283148805132706929678095239979 79
UVM_INFO @ 88578303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 23078405576941371216518939207255849575156194587126786817926994299410692985475 78
UVM_INFO @ 6548934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 27559554460378576129075503923195661737666667495010691684138752627246192765341 81
UVM_INFO @ 2089565576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 15466617224313762214004713595943259127506439941255953249028691561492666932294 78
UVM_INFO @ 3300920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 8330761234359749619598197332497146636153311116540728313304250810234180749465 80
UVM_INFO @ 489186091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 30291700217313258538152536478210300264084622063202178872003131451924626248286 78
UVM_INFO @ 6873359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 67426794294872291975841830258830397198446968104957798875155546655667949086726 78
UVM_INFO @ 1870419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:649) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 6 test runs
gpio_same_csr_outstanding 68103760491088203664176600848328748040478300237958360233309450417426926223455 77
UVM_INFO @ 92562743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_same_csr_outstanding 106833608909481459313192319579535040781553275624340477674258416340833892394098 77
UVM_INFO @ 12693100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_same_csr_outstanding 1714681139631381328061066494278975834741498891723099714793832458635904620574 77
UVM_INFO @ 8239772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_same_csr_outstanding 70073444324697410574822721495129519032781266061483599467430066261937719517778 77
UVM_INFO @ 69066883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_same_csr_outstanding 6371095941324219715554095129165300220601774856063922321287191339697452369668 77
UVM_INFO @ 19279353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_same_csr_outstanding 51742591821308401346811262737648937741819872155812933850902698920878125131493 76
UVM_INFO @ 132523175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_*.enable reset value: * 1 test run
gpio_tl_intg_err 26055480327643928237702936640303298016445017927346040038904514105072314676247 281
UVM_INFO @ 911514024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_* reset value: * 1 test run
gpio_tl_intg_err 83873463988383108946844567307455482698445148442231051243635726514152614917156 83
UVM_INFO @ 5337485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---