Simulation Results: hmac

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.54 %
  • code
  • 96.11 %
  • assert
  • 96.51 %
  • func
  • 100.00 %
  • block
  • 97.69 %
  • line
  • 98.44 %
  • branch
  • 94.23 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 15.000s 751.657us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 2.000s 162.979us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 2.000s 44.883us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 15.000s 1111.082us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 7.000s 579.705us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 961.000s 1834571.272us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 2.000s 44.883us 20 20 100.00
hmac_csr_aliasing 7.000s 579.705us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 109.000s 92608.898us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 116.000s 3558.031us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 304.000s 24130.786us 30 30 100.00
hmac_test_sha384_vectors 656.000s 13859.705us 75 75 100.00
hmac_test_sha512_vectors 630.000s 43058.500us 75 75 100.00
hmac_test_hmac256_vectors 21.000s 426.214us 50 50 100.00
hmac_test_hmac384_vectors 22.000s 402.846us 60 60 100.00
hmac_test_hmac512_vectors 36.000s 373.293us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 56.000s 4105.995us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 344.000s 22503.157us 10 10 100.00
error 10 10 100.00
hmac_error 130.000s 18904.695us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 116.000s 2608.846us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 15.000s 751.657us 10 10 100.00
hmac_long_msg 109.000s 92608.898us 10 10 100.00
hmac_back_pressure 116.000s 3558.031us 25 25 100.00
hmac_datapath_stress 344.000s 22503.157us 10 10 100.00
hmac_burst_wr 56.000s 4105.995us 50 50 100.00
hmac_stress_all 803.000s 52460.873us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 15.000s 751.657us 10 10 100.00
hmac_long_msg 109.000s 92608.898us 10 10 100.00
hmac_back_pressure 116.000s 3558.031us 25 25 100.00
hmac_datapath_stress 344.000s 22503.157us 10 10 100.00
hmac_wipe_secret 116.000s 2608.846us 10 10 100.00
hmac_test_sha256_vectors 304.000s 24130.786us 30 30 100.00
hmac_test_sha384_vectors 656.000s 13859.705us 75 75 100.00
hmac_test_sha512_vectors 630.000s 43058.500us 75 75 100.00
hmac_test_hmac256_vectors 21.000s 426.214us 50 50 100.00
hmac_test_hmac384_vectors 22.000s 402.846us 60 60 100.00
hmac_test_hmac512_vectors 36.000s 373.293us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 15.000s 751.657us 10 10 100.00
hmac_long_msg 109.000s 92608.898us 10 10 100.00
hmac_back_pressure 116.000s 3558.031us 25 25 100.00
hmac_datapath_stress 344.000s 22503.157us 10 10 100.00
hmac_burst_wr 56.000s 4105.995us 50 50 100.00
hmac_error 130.000s 18904.695us 10 10 100.00
hmac_wipe_secret 116.000s 2608.846us 10 10 100.00
hmac_test_sha256_vectors 304.000s 24130.786us 30 30 100.00
hmac_test_sha384_vectors 656.000s 13859.705us 75 75 100.00
hmac_test_sha512_vectors 630.000s 43058.500us 75 75 100.00
hmac_test_hmac256_vectors 21.000s 426.214us 50 50 100.00
hmac_test_hmac384_vectors 22.000s 402.846us 60 60 100.00
hmac_test_hmac512_vectors 36.000s 373.293us 75 75 100.00
hmac_stress_all 803.000s 52460.873us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 803.000s 52460.873us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 2.000s 40.727us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 2.000s 40.749us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 5.000s 118.394us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 5.000s 118.394us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 2.000s 162.979us 5 5 100.00
hmac_csr_rw 2.000s 44.883us 20 20 100.00
hmac_csr_aliasing 7.000s 579.705us 5 5 100.00
hmac_same_csr_outstanding 4.000s 294.251us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 2.000s 162.979us 5 5 100.00
hmac_csr_rw 2.000s 44.883us 20 20 100.00
hmac_csr_aliasing 7.000s 579.705us 5 5 100.00
hmac_same_csr_outstanding 4.000s 294.251us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 2.000s 253.457us 5 5 100.00
hmac_tl_intg_err 6.000s 3575.908us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 6.000s 3575.908us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 15.000s 751.657us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 9.000s 1878.664us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 851.000s 60762.325us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 5.000s 242.595us 1 1 100.00