Simulation Results: kmac/masked

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.83 %
  • code
  • 94.53 %
  • assert
  • 97.98 %
  • func
  • 97.99 %
  • line
  • 99.25 %
  • branch
  • 97.08 %
  • cond
  • 94.76 %
  • toggle
  • 99.89 %
  • FSM
  • 81.69 %
Validation stages
V1
100.00%
V2
100.00%
V2S
99.56%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 91.380s 20987.067us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.550s 115.833us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.530s 35.322us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 16.700s 4993.646us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 8.680s 2015.342us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.390s 38.596us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.530s 35.322us 20 20 100.00
kmac_csr_aliasing 8.680s 2015.342us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.150s 19.943us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.740s 163.812us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 4217.210s 359943.592us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1263.700s 35220.921us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2696.170s 94518.284us 5 5 100.00
kmac_test_vectors_sha3_256 2276.920s 59701.099us 5 5 100.00
kmac_test_vectors_sha3_384 1547.980s 45410.902us 5 5 100.00
kmac_test_vectors_sha3_512 914.440s 39567.164us 5 5 100.00
kmac_test_vectors_shake_128 3116.960s 116287.545us 5 5 100.00
kmac_test_vectors_shake_256 2454.970s 87396.255us 5 5 100.00
kmac_test_vectors_kmac 3.110s 101.538us 5 5 100.00
kmac_test_vectors_kmac_xof 3.310s 188.435us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 484.450s 82795.133us 50 50 100.00
app 50 50 100.00
kmac_app 385.850s 18460.937us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 297.250s 27109.093us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 322.980s 18762.181us 50 50 100.00
error 50 50 100.00
kmac_error 453.030s 18814.954us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 17.360s 8342.997us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 9.140s 273.684us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 44.160s 11309.092us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 30.690s 469.004us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 64.170s 24968.921us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 37.060s 1832.539us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 3066.720s 352151.596us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.220s 15.366us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.250s 33.084us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.930s 866.966us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.930s 866.966us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.550s 115.833us 5 5 100.00
kmac_csr_rw 1.530s 35.322us 20 20 100.00
kmac_csr_aliasing 8.680s 2015.342us 5 5 100.00
kmac_same_csr_outstanding 2.280s 76.357us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.550s 115.833us 5 5 100.00
kmac_csr_rw 1.530s 35.322us 20 20 100.00
kmac_csr_aliasing 8.680s 2015.342us 5 5 100.00
kmac_same_csr_outstanding 2.280s 76.357us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.930s 96.509us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.930s 96.509us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.930s 96.509us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.930s 96.509us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 6.000s 504.006us 19 20 95.00
tl_intg_err 25 25 100.00
kmac_sec_cm 65.650s 16238.956us 5 5 100.00
kmac_tl_intg_err 5.060s 621.072us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.060s 621.072us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 37.060s 1832.539us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 91.380s 20987.067us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 484.450s 82795.133us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.930s 96.509us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 65.650s 16238.956us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 65.650s 16238.956us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 65.650s 16238.956us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 91.380s 20987.067us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 37.060s 1832.539us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 65.650s 16238.956us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 336.580s 95358.189us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 91.380s 20987.067us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 261.470s 4550.173us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 1 test run
kmac_stress_all_with_rand_reset 83620186463364663595625741640747095958155458238068316942876131326010059248160 197
UVM_INFO @ 565310512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * 1 test run
kmac_shadow_reg_errors_with_csr_rw 93724610616500459002710130750675215343762725528693352560149079574051665297348 93
UVM_INFO @ 8355231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---