Simulation Results: kmac/unmasked

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.50 %
  • code
  • 92.22 %
  • assert
  • 97.90 %
  • func
  • 96.39 %
  • line
  • 97.65 %
  • branch
  • 95.93 %
  • cond
  • 94.79 %
  • toggle
  • 100.00 %
  • FSM
  • 72.73 %
Validation stages
V1
100.00%
V2
98.31%
V2S
99.56%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 58.870s 27566.992us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.520s 107.062us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.560s 34.107us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 19.750s 7991.530us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 9.210s 2092.549us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.110s 1026.979us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.560s 34.107us 20 20 100.00
kmac_csr_aliasing 9.210s 2092.549us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.060s 41.291us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.840s 217.268us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 4288.880s 126520.039us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 897.800s 35271.256us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2323.980s 572103.804us 5 5 100.00
kmac_test_vectors_sha3_256 1346.740s 89009.631us 5 5 100.00
kmac_test_vectors_sha3_384 1572.140s 230934.372us 5 5 100.00
kmac_test_vectors_sha3_512 667.240s 9272.335us 5 5 100.00
kmac_test_vectors_shake_128 1632.490s 77048.345us 5 5 100.00
kmac_test_vectors_shake_256 1810.220s 60267.338us 5 5 100.00
kmac_test_vectors_kmac 3.010s 594.203us 5 5 100.00
kmac_test_vectors_kmac_xof 2.930s 378.771us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 459.850s 300399.251us 50 50 100.00
app 50 50 100.00
kmac_app 272.510s 57950.620us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 249.240s 58024.248us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 335.380s 219299.598us 50 50 100.00
error 50 50 100.00
kmac_error 346.240s 73664.342us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 16.310s 13032.932us 50 50 100.00
sideload_invalid 37 50 74.00
kmac_sideload_invalid 148.620s 10079.602us 37 50 74.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 37.190s 2202.519us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 35.580s 2519.666us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 43.380s 14693.885us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 41.720s 1666.205us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 3315.490s 262153.210us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.210s 206.084us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.230s 29.898us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.320s 557.866us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.320s 557.866us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.520s 107.062us 5 5 100.00
kmac_csr_rw 1.560s 34.107us 20 20 100.00
kmac_csr_aliasing 9.210s 2092.549us 5 5 100.00
kmac_same_csr_outstanding 3.280s 1213.891us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.520s 107.062us 5 5 100.00
kmac_csr_rw 1.560s 34.107us 20 20 100.00
kmac_csr_aliasing 9.210s 2092.549us 5 5 100.00
kmac_same_csr_outstanding 3.280s 1213.891us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.900s 84.111us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.900s 84.111us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.900s 84.111us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.900s 84.111us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 6.120s 1432.786us 19 20 95.00
tl_intg_err 25 25 100.00
kmac_sec_cm 57.670s 10008.730us 5 5 100.00
kmac_tl_intg_err 5.780s 965.613us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.780s 965.613us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 41.720s 1666.205us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 58.870s 27566.992us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 459.850s 300399.251us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.900s 84.111us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 57.670s 10008.730us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 57.670s 10008.730us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 57.670s 10008.730us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 58.870s 27566.992us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 41.720s 1666.205us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 57.670s 10008.730us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 255.080s 17560.352us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 58.870s 27566.992us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 255.020s 18394.164us 9 10 90.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) 4 test runs
kmac_sideload_invalid 84676960094764062904193504156306136455893006569428595689671433815908627726546 83
UVM_INFO @ 10279800684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 95820184095428104719734367194700247690728696492502213949992706553444361566711 83
UVM_INFO @ 10256532548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 61480211751310620230095112596482302001475732147441911570116588927694048762448 83
UVM_INFO @ 10067753407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 53583363178933514787644087354737316904094915092841449340543438659155150000073 83
UVM_INFO @ 10085586435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) 2 test runs
kmac_sideload_invalid 100484011301371314144951536820267000944227662652570685516466247143216575070832 80
UVM_INFO @ 10043116465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 14937486088669526215820407716147257703200347849569087294150969393944236210101 81
UVM_INFO @ 10105184253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) 1 test run
kmac_sideload_invalid 12802319908373334554954151493160689088978595965091398155004160124812623395991 89
UVM_INFO @ 10146962225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
kmac_stress_all_with_rand_reset 50558615237081323618812757367763303353461825779337825589316262967178164750464 204
UVM_INFO @ 2064371664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * 1 test run
kmac_shadow_reg_errors_with_csr_rw 21138223564729031979287006469267950304217772190642024220405432563045232539073 155
UVM_INFO @ 57083006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) 1 test run
kmac_sideload_invalid 86599695664100349817431360279334450545158260926050607561740273062648683769313 92
UVM_INFO @ 10079602303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) 1 test run
kmac_sideload_invalid 96540094948544509213288492920794786215330353710495767079090748602831473144233 86
UVM_INFO @ 10065115500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) 1 test run
kmac_sideload_invalid 97219438725898472501734160064537830888690916240986278168305824006665890567557 97
UVM_INFO @ 10109364272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) 1 test run
kmac_sideload_invalid 4738433435928848203043138726469389515558955451600313641511691561097133123412 78
UVM_INFO @ 10008357768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) 1 test run
kmac_sideload_invalid 89275593709161040864181297330018660952332808434942617381429440625948942576717 82
UVM_INFO @ 10362175282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) 1 test run
kmac_sideload_invalid 25053260603870579791090413055630640588307770720977154612133361058937504953271 95
UVM_INFO @ 10072662329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---