Simulation Results: lc_ctrl/volatile_unlock_disabled

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.80 %
  • code
  • 93.58 %
  • assert
  • 95.97 %
  • func
  • 88.85 %
  • block
  • 96.75 %
  • line
  • 97.38 %
  • branch
  • 91.72 %
  • toggle
  • 89.97 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.04%
V2S
99.72%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 5.000s 539.549us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 26.000s 20.817us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 25.000s 44.783us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 26.000s 69.346us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 26.000s 45.894us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 25.000s 17.468us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 25.000s 44.783us 20 20 100.00
lc_ctrl_csr_aliasing 26.000s 45.894us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 4.000s 355.778us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 15.000s 406.253us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 26.000s 14.491us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.000s 126.460us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 10.000s 1627.189us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 27.000s 1378.137us 50 50 100.00
security_escalation 256 260 98.46
lc_ctrl_state_failure 10.000s 1627.189us 50 50 100.00
lc_ctrl_prog_failure 4.000s 126.460us 50 50 100.00
lc_ctrl_errors 27.000s 1378.137us 50 50 100.00
lc_ctrl_security_escalation 10.000s 838.841us 50 50 100.00
lc_ctrl_jtag_state_failure 82.000s 4497.537us 17 20 85.00
lc_ctrl_jtag_prog_failure 16.000s 930.176us 20 20 100.00
lc_ctrl_jtag_errors 54.000s 6353.656us 19 20 95.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 10.000s 1677.601us 20 20 100.00
lc_ctrl_jtag_state_post_trans 25.000s 1455.595us 19 20 95.00
lc_ctrl_jtag_prog_failure 16.000s 930.176us 20 20 100.00
lc_ctrl_jtag_errors 54.000s 6353.656us 19 20 95.00
lc_ctrl_jtag_access 26.000s 322.938us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 19.000s 5228.820us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 12.000s 679.008us 10 10 100.00
lc_ctrl_jtag_csr_rw 10.000s 811.664us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 32.000s 983.598us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 26.000s 1195.352us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 164.686us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 11.000s 637.060us 10 10 100.00
lc_ctrl_jtag_alert_test 25.000s 445.627us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 32.000s 9076.960us 10 10 100.00
lc_ctrl_volatile_unlock 49 50 98.00
lc_ctrl_volatile_unlock_smoke 2.000s 90.137us 49 50 98.00
stress_all 49 50 98.00
lc_ctrl_stress_all 400.000s 19232.079us 49 50 98.00
alert_test 50 50 100.00
lc_ctrl_alert_test 26.000s 15.677us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 6.000s 375.388us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 6.000s 375.388us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 26.000s 20.817us 5 5 100.00
lc_ctrl_csr_rw 25.000s 44.783us 20 20 100.00
lc_ctrl_csr_aliasing 26.000s 45.894us 5 5 100.00
lc_ctrl_same_csr_outstanding 3.000s 106.544us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 26.000s 20.817us 5 5 100.00
lc_ctrl_csr_rw 25.000s 44.783us 20 20 100.00
lc_ctrl_csr_aliasing 26.000s 45.894us 5 5 100.00
lc_ctrl_same_csr_outstanding 3.000s 106.544us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 7.000s 1061.553us 5 5 100.00
lc_ctrl_tl_intg_err 4.000s 149.120us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 4.000s 149.120us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 15.000s 406.253us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 10.000s 1627.189us 50 50 100.00
lc_ctrl_sec_cm 7.000s 1061.553us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 10.000s 1627.189us 50 50 100.00
lc_ctrl_sec_cm 7.000s 1061.553us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 10.000s 1627.189us 50 50 100.00
lc_ctrl_sec_cm 7.000s 1061.553us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 10.000s 1627.189us 50 50 100.00
lc_ctrl_sec_cm 7.000s 1061.553us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 10.000s 1627.189us 50 50 100.00
lc_ctrl_sec_cm 7.000s 1061.553us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 10.000s 1627.189us 50 50 100.00
lc_ctrl_sec_cm 7.000s 1061.553us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 10.000s 1627.189us 50 50 100.00
lc_ctrl_sec_cm 7.000s 1061.553us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 10.000s 1627.189us 50 50 100.00
lc_ctrl_sec_cm 7.000s 1061.553us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 10.000s 838.841us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 69 70 98.57
lc_ctrl_state_post_trans 4.000s 355.778us 50 50 100.00
lc_ctrl_jtag_state_post_trans 25.000s 1455.595us 19 20 95.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 14.000s 477.750us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 14.000s 477.750us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 12.000s 381.236us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 14.000s 3531.334us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 14.000s 3531.334us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 25 50 50.00
lc_ctrl_stress_all_with_rand_reset 94.000s 4159.925us 25 50 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 23 test runs
lc_ctrl_stress_all_with_rand_reset 5312639455048883067605044187583830113787576641650945623279227553179766893447 959
UVM_INFO @ 3831660260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 16235183349388077380420791308809768270248974878722262218331447709505176144652 2880
UVM_INFO @ 4898346874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 70349156588734262573049196316883733880999490423764304813889827966588410945910 612
UVM_INFO @ 1085982758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 31773219265141800894731648988606760145407405343021267207271031167764974390104 3614
UVM_INFO @ 32317941604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 29215112719704716047537958278180915030925817299404538721140225347079096596446 243
UVM_INFO @ 4748260673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 14588411103332527616101415871908255474777013902492827970825956618892948226652 653
UVM_INFO @ 7091364797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 73133664413199725151377087227153089673245107746392668524226479131494116570936 4719
UVM_INFO @ 1928772548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 92211385205494845062243605985243283352497299407838211005889693722586269643222 5952
UVM_INFO @ 3100520448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 81196908468160782322971944513951892380155689180194503212043653102437330749482 1464
UVM_INFO @ 1526253270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 10556230446957229819957832783113746822302799954521901415741641890974117890479 1383
UVM_INFO @ 4944858200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 54837336051840122928920483066015328506579318523360736601124754534328260091243 723
UVM_INFO @ 325730469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 68288805481099658199436507659984742958179688838180700275291967236720714889162 163
UVM_INFO @ 556160951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 94533866305904111440716857328403895590242688952561291547730808626689496743033 1747
UVM_INFO @ 3284976005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 82687530025693993301470591677968632349862921385152719723926654579229723372803 160
UVM_INFO @ 112854396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 41873275157180240649724776882842689565418380791076784856758735704584210572806 2446
UVM_INFO @ 4824664550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 10299941942064885802875414863177240159987537181346719144149204498289041133847 532
UVM_INFO @ 1758438778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 29466822762008433585826396024825453686208044708003570194700573986729297584434 2110
UVM_INFO @ 3108475488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 91493259978922523186876129820435172755685567875080310212412967115593329140330 468
UVM_INFO @ 1986516838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 9829405024088547560328437731784503174395390814192734343906775187510472284557 4055
UVM_INFO @ 18607954622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 9587793297988320525705831327839207562858341666608036867095582734194074054407 181
UVM_INFO @ 104353850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 67959686835896002004794615390133025707488295950269955439379080461320884878171 192
UVM_INFO @ 321396764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 113845398376502144472319684618102142406483259678435395598047088797519592988716 4978
UVM_INFO @ 13724290897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 82973611046505119676420632248635897258163443517885594353077418536262398883598 4168
UVM_INFO @ 4117709853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 4 test runs
lc_ctrl_jtag_state_failure 46311300707328388396937608749123226304214652382739873117081390702382501019515 177
UVM_INFO @ 49735340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 46939468240696795325954860797462461679438490754954744338445365005392284691044 179
UVM_INFO @ 120271954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 81297176134823863209766943276588518129226576585777591220757201441314068579343 177
UVM_INFO @ 13981518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 88778469736059933155214255255630289571873255739635831582171293139916177235093 177
UVM_INFO @ 17640705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 2 test runs
lc_ctrl_jtag_errors 1645669765687515858664736933488814350949342063706263430981808941194644627693 547
UVM_INFO @ 1306733554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 83573378077176321594643928924991149447238422839968251719088136736823002983571 1673
UVM_INFO @ 2090775047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* 1 test run
lc_ctrl_stress_all 20825331836153798130444281845055378001952780366019387904321260999437787045633 400
UVM_INFO @ 582503738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout lc_ctrl_regs_reg_block.status.token_error (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
lc_ctrl_volatile_unlock_smoke 62323564308051085301810229226306135666074087937597325612823011127466689095483 157
UVM_INFO @ 121252304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 62365628263796249641530890103259300944469809460850043710187023618272914315302 4928
UVM_INFO @ 4159924986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---