Simulation Results: lc_ctrl/volatile_unlock_enabled

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.56 %
  • code
  • 94.59 %
  • assert
  • 95.97 %
  • func
  • 90.13 %
  • block
  • 97.25 %
  • line
  • 97.72 %
  • branch
  • 93.02 %
  • toggle
  • 89.99 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
98.77%
V2S
99.72%
V3
42.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 5.000s 210.111us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 2.000s 17.848us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 2.000s 45.862us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 3.000s 93.476us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 97.482us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 3.000s 111.119us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 2.000s 45.862us 20 20 100.00
lc_ctrl_csr_aliasing 2.000s 97.482us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 5.000s 632.659us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 11.000s 1865.678us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 2.000s 38.881us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 5.000s 111.951us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 8.000s 357.755us 50 50 100.00
lc_errors 50 50 100.00
lc_ctrl_errors 12.000s 9848.525us 50 50 100.00
security_escalation 254 260 97.69
lc_ctrl_state_failure 8.000s 357.755us 50 50 100.00
lc_ctrl_prog_failure 5.000s 111.951us 50 50 100.00
lc_ctrl_errors 12.000s 9848.525us 50 50 100.00
lc_ctrl_security_escalation 9.000s 802.439us 50 50 100.00
lc_ctrl_jtag_state_failure 62.000s 9707.957us 18 20 90.00
lc_ctrl_jtag_prog_failure 16.000s 871.520us 16 20 80.00
lc_ctrl_jtag_errors 65.000s 8054.225us 20 20 100.00
jtag_access 205 210 97.62
lc_ctrl_jtag_smoke 9.000s 3398.745us 20 20 100.00
lc_ctrl_jtag_state_post_trans 16.000s 777.697us 19 20 95.00
lc_ctrl_jtag_prog_failure 16.000s 871.520us 16 20 80.00
lc_ctrl_jtag_errors 65.000s 8054.225us 20 20 100.00
lc_ctrl_jtag_access 20.000s 19244.619us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 25.000s 1254.098us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 133.702us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.000s 294.563us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 13.000s 758.552us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 22.000s 6201.733us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 42.531us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.000s 1230.785us 10 10 100.00
lc_ctrl_jtag_alert_test 3.000s 103.924us 10 10 100.00
jtag_priority 9 10 90.00
lc_ctrl_jtag_priority 21.000s 27757.923us 9 10 90.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 43.764us 50 50 100.00
stress_all 49 50 98.00
lc_ctrl_stress_all 303.000s 56706.395us 49 50 98.00
alert_test 50 50 100.00
lc_ctrl_alert_test 3.000s 83.408us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 7.000s 998.320us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 7.000s 998.320us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 2.000s 17.848us 5 5 100.00
lc_ctrl_csr_rw 2.000s 45.862us 20 20 100.00
lc_ctrl_csr_aliasing 2.000s 97.482us 5 5 100.00
lc_ctrl_same_csr_outstanding 3.000s 40.732us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 2.000s 17.848us 5 5 100.00
lc_ctrl_csr_rw 2.000s 45.862us 20 20 100.00
lc_ctrl_csr_aliasing 2.000s 97.482us 5 5 100.00
lc_ctrl_same_csr_outstanding 3.000s 40.732us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 5.000s 234.136us 5 5 100.00
lc_ctrl_tl_intg_err 4.000s 524.674us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 4.000s 524.674us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 11.000s 1865.678us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 8.000s 357.755us 50 50 100.00
lc_ctrl_sec_cm 5.000s 234.136us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 8.000s 357.755us 50 50 100.00
lc_ctrl_sec_cm 5.000s 234.136us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 8.000s 357.755us 50 50 100.00
lc_ctrl_sec_cm 5.000s 234.136us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 8.000s 357.755us 50 50 100.00
lc_ctrl_sec_cm 5.000s 234.136us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 8.000s 357.755us 50 50 100.00
lc_ctrl_sec_cm 5.000s 234.136us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 8.000s 357.755us 50 50 100.00
lc_ctrl_sec_cm 5.000s 234.136us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 8.000s 357.755us 50 50 100.00
lc_ctrl_sec_cm 5.000s 234.136us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 8.000s 357.755us 50 50 100.00
lc_ctrl_sec_cm 5.000s 234.136us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 9.000s 802.439us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 69 70 98.57
lc_ctrl_state_post_trans 5.000s 632.659us 50 50 100.00
lc_ctrl_jtag_state_post_trans 16.000s 777.697us 19 20 95.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 15.000s 1001.559us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 15.000s 1001.559us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 17.000s 780.428us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 13.000s 2263.919us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 13.000s 2263.919us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 21 50 42.00
lc_ctrl_stress_all_with_rand_reset 124.000s 36946.480us 21 50 42.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 23 test runs
lc_ctrl_stress_all_with_rand_reset 79274842539082651421794906665109965313916727364595939169692012909775311792415 181
UVM_INFO @ 353578682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 96154460288717476784148476484547165976288120127199572299763323784016215560749 519
UVM_INFO @ 1742662762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 52494044269902081105290800165827993960644693485158058589105877957663178265354 1600
UVM_INFO @ 4080647267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 94335162697998328387632026759086613765300041873700839075468261314631514572626 1408
UVM_INFO @ 5407233591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 66308580202616591536369736779865130888575599924587227620581830333894244903219 1426
UVM_INFO @ 2577419875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 39451899562377806904932359025096897192038495444775602333075939531320597408886 7033
UVM_INFO @ 16592282730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 81259465155531881434827258652171869872005105046188221305166911008496473686370 6314
UVM_INFO @ 4580121504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 64126179906151632684672158437267577782584445736433004270721823965928425301832 3382
UVM_INFO @ 36946479686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 66169524939848680761929793573508273152772554932754920386572234673844919125857 264
UVM_INFO @ 1473524445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 48697290980442579709853760803986227381176856550702093159717207652960762201148 165
UVM_INFO @ 994963082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 63192056037248643962219837347885229012256702025927545142086193880482377177080 1264
UVM_INFO @ 1145222242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 19428379591397441418286192751725188658370719017123577872144110133481418192586 2865
UVM_INFO @ 6533306892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 105884587824001002015622756007360013496498028407825446711221515371363386575713 160
UVM_INFO @ 216521543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 43762318829814213207709845595621981797195544299581037179363999984672444150900 1750
UVM_INFO @ 4378433065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 28687928235298806917157537783365118348750191655748468098396728069566752526904 3545
UVM_INFO @ 3609799741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 43341476297296505433339916319621370864774757327086256106690508198274934580060 3118
UVM_INFO @ 1797331773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 58074081975983442089890903285727241068842041509413009782231888817140375077102 1952
UVM_INFO @ 1934940701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 47089732802369999510880987088758218774366697470918623650865316600417635737046 263
UVM_INFO @ 409294683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 107139782959814428355008313063155265482526507223815826287793432004711790982604 2103
UVM_INFO @ 1800038776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 7763428959666900014393411889114142346377347867968537967069027555599663014229 488
UVM_INFO @ 5983332063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 23157579052220148978895994175138479328517457742493147808322629759400626932751 160
UVM_INFO @ 161304938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 35632911879707560057375080530824790689867076553307500776468639505852923583128 161
UVM_INFO @ 197051288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 29260454814462262000813851664681564084357305289048497538521671377330049097914 165
UVM_INFO @ 252401230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 5 test runs
lc_ctrl_stress_all_with_rand_reset 78187096178666757579740656473096005189865640174803415111664436510404960481863 4822
UVM_INFO @ 24044800181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 25472297350252941007393910380960546343131733101643732595231626913606466589954 4005
UVM_INFO @ 2918157366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 98615152120206947898581810512726941640060297688163157157025107935344199108605 1803
UVM_INFO @ 1881646819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 5472827753169986879444617212000148583738716583896466768938596879997589913855 1952
UVM_INFO @ 3533629217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 67739395428250708837204368337430222992419608035260999864897910685089352556742 4220
UVM_INFO @ 7449636326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 4 test runs
lc_ctrl_jtag_prog_failure 105754427824548681014671244324485859337855074655214798246310496540320983355848 178
UVM_INFO @ 254574430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 71141989151543108719192620775078811199829287486166737476639771826003894718800 177
UVM_INFO @ 44302690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 99915092295547625566528135093934035024845598618462030786590205010885958225643 178
UVM_INFO @ 281516564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 48426747261972429394582846145344668565292010033903020395467460982580532725771 178
UVM_INFO @ 362793213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 3 test runs
lc_ctrl_jtag_state_post_trans 67767648576497641893448660650443946102407093300477300253745766520957349599970 177
UVM_INFO @ 33321488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 94479714359272293338344602995267807113371788709531468781341779007388213033796 177
UVM_INFO @ 44676901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 92080274299432594638404510994316782972459983340543474965413899995582514309758 177
UVM_INFO @ 898726649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [lc_ctrl_common_vseq] wait timeout occurred! 1 test run
lc_ctrl_stress_all_with_rand_reset 3535192770126678636779240019186417501721516346049762784361600611973036712340 1488
UVM_INFO @ 11208078946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:136) [lc_ctrl_jtag_priority_vseq] wait for simultaneous mutex claim 1 test run
lc_ctrl_jtag_priority 8828413587094451090088399361616699043856031124721104445003141839282537189255 157
UVM_INFO @ 27757922590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_stress_all 90060590828971271796269793774052227587387449768066497598874728245855771404459 3631
UVM_INFO @ 1744087119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---