Simulation Results: otbn

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.86 %
  • code
  • 96.64 %
  • assert
  • 96.95 %
  • func
  • 100.00 %
  • block
  • 99.48 %
  • line
  • 99.60 %
  • branch
  • 93.32 %
  • toggle
  • 93.65 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.46%
V2S
95.28%
V3
40.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 13.000s 42.773us 1 1 100.00
single_binary 100 100 100.00
otbn_single 36.000s 130.663us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 8.000s 15.165us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 8.000s 23.391us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 11.000s 221.871us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 8.000s 41.058us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 10.000s 255.270us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 8.000s 23.391us 20 20 100.00
otbn_csr_aliasing 8.000s 41.058us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 125.000s 14392.750us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 55.000s 5552.650us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 44.000s 575.015us 10 10 100.00
multi_error 0 1 0.00
otbn_multi_err 19.000s 214.069us 0 1 0.00
back_to_back 8 10 80.00
otbn_multi 268.000s 4306.065us 8 10 80.00
stress_all 10 10 100.00
otbn_stress_all 165.000s 1389.731us 10 10 100.00
lc_escalation 57 60 95.00
otbn_escalate 25.000s 88.048us 57 60 95.00
zero_state_err_urnd 4 5 80.00
otbn_zero_state_err_urnd 9.000s 17.684us 4 5 80.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 22.000s 55.701us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 9.000s 16.114us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 8.000s 34.963us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 9.000s 93.799us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 9.000s 93.799us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 8.000s 15.165us 5 5 100.00
otbn_csr_rw 8.000s 23.391us 20 20 100.00
otbn_csr_aliasing 8.000s 41.058us 5 5 100.00
otbn_same_csr_outstanding 7.000s 34.536us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 8.000s 15.165us 5 5 100.00
otbn_csr_rw 8.000s 23.391us 20 20 100.00
otbn_csr_aliasing 8.000s 41.058us 5 5 100.00
otbn_same_csr_outstanding 7.000s 34.536us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 11.000s 40.059us 10 10 100.00
otbn_dmem_err 17.000s 67.426us 15 15 100.00
internal_integrity 16 17 94.12
otbn_alu_bignum_mod_err 11.000s 120.975us 4 5 80.00
otbn_controller_ispr_rdata_err 22.000s 226.318us 5 5 100.00
otbn_mac_bignum_acc_err 12.000s 73.604us 5 5 100.00
otbn_urnd_err 6.000s 19.021us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 7.000s 15.960us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 7.000s 22.709us 2 2 100.00
otbn_non_sec_partial_wipe 8 10 80.00
otbn_partial_wipe 8.000s 133.796us 8 10 80.00
tl_intg_err 25 25 100.00
otbn_sec_cm 284.000s 1812.252us 5 5 100.00
otbn_tl_intg_err 32.000s 185.406us 20 20 100.00
passthru_mem_tl_intg_err 17 20 85.00
otbn_passthru_mem_tl_intg_err 52.000s 725.837us 17 20 85.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 284.000s 1812.252us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 284.000s 1812.252us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 13.000s 42.773us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 17.000s 67.426us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 11.000s 40.059us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 32.000s 185.406us 20 20 100.00
sec_cm_controller_fsm_global_esc 57 60 95.00
otbn_escalate 25.000s 88.048us 57 60 95.00
sec_cm_controller_fsm_local_esc 39 40 97.50
otbn_imem_err 11.000s 40.059us 10 10 100.00
otbn_dmem_err 17.000s 67.426us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 17.684us 4 5 80.00
otbn_illegal_mem_acc 7.000s 15.960us 5 5 100.00
otbn_sec_cm 284.000s 1812.252us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 284.000s 1812.252us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 36.000s 130.663us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 11.000s 40.059us 10 10 100.00
otbn_dmem_err 17.000s 67.426us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 17.684us 4 5 80.00
otbn_illegal_mem_acc 7.000s 15.960us 5 5 100.00
otbn_sec_cm 284.000s 1812.252us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 284.000s 1812.252us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 57 60 95.00
otbn_escalate 25.000s 88.048us 57 60 95.00
sec_cm_start_stop_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 11.000s 40.059us 10 10 100.00
otbn_dmem_err 17.000s 67.426us 15 15 100.00
otbn_zero_state_err_urnd 9.000s 17.684us 4 5 80.00
otbn_illegal_mem_acc 7.000s 15.960us 5 5 100.00
otbn_sec_cm 284.000s 1812.252us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 284.000s 1812.252us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 36.000s 130.663us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 11.000s 45.753us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 13.000s 50.638us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 53.000s 467.107us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 53.000s 467.107us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 10.000s 37.910us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 284.000s 1812.252us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 284.000s 1812.252us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 8 10 80.00
otbn_rf_bignum_intg_err 13.000s 75.864us 8 10 80.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 284.000s 1812.252us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 284.000s 1812.252us 5 5 100.00
sec_cm_loop_stack_addr_integrity 3 5 60.00
otbn_stack_addr_integ_chk 10.000s 27.789us 3 5 60.00
sec_cm_call_stack_addr_integrity 3 5 60.00
otbn_stack_addr_integ_chk 10.000s 27.789us 3 5 60.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 14.000s 122.258us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 36.000s 130.663us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 36.000s 130.663us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 36.000s 130.663us 100 100 100.00
sec_cm_write_mem_integrity 8 10 80.00
otbn_multi 268.000s 4306.065us 8 10 80.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 36.000s 130.663us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 36.000s 130.663us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 20.000s 173.530us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 36.000s 130.663us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 284.000s 1812.252us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
otbn_stress_all_with_rand_reset 596.000s 8049.881us 4 10 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 9.000s 77.104us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 6 test runs
otbn_zero_state_err_urnd 5052977064293024947911271594534948387421056224912942542457017492976536197509 112
UVM_ERROR @ 77927605 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 77927605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stack_addr_integ_chk 51969963362054482323974711873316993501769277031144522570565829818928254455743 121
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 19951762 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 19951762 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 19951762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stack_addr_integ_chk 98077217779095098307342100283985366638634087060412972115077850880397378079175 115
UVM_ERROR @ 16284439 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 16284439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 19400556450899496670268765909144050440645121529610531515069459718570936023281 964
UVM_ERROR @ 8049880509 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 8049880509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 12851988833166599733083135719468977708520893903107945104400856909754578785092 113
UVM_ERROR @ 17796698 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 17796698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 53472613783106050674285806418323409920660946029817420518597431516454579837709 115
UVM_ERROR @ 23695437 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 23695437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 4 test runs
otbn_multi_err 62251463401748659506526509193733897015101478606654698682700392443518953416658 282
UVM_INFO @ 214068784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_multi 97987570268585650435475895619540103350177320966890872360483653150776119110374 181
UVM_INFO @ 1328025591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 40019865899329890002277345772814546123275006355673924897979331220965029205190 106
UVM_INFO @ 64829433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 31984088223370913069747864697613599581013819363877223513278533081117029985765 86
UVM_INFO @ 1216181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
otbn_stress_all_with_rand_reset 50772713648217648926239804710041880433162268945320540843570869412518644162694 159
UVM_INFO @ 659967912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 45734664594639528841660582034185472580804437873912113255325764084799219416315 147
UVM_INFO @ 471699407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 48000164116304910877580861518541500206513918781727902730040131884266552818270 259
UVM_INFO @ 931400443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 93002415469730931786057050582317266738349934164824053379292282653430595565488 262
UVM_INFO @ 2829823761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 3 test runs
otbn_alu_bignum_mod_err 8811860563715160441441411841797526410040580670513026155586409261205928932198 121
UVM_INFO @ 45076411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 88176533312418414198082919094374894336034566529139088218929230512864192400228 113
UVM_INFO @ 40580455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 82507402131210507917689656747597699757848871811227864223435704982850860583635 110
UVM_INFO @ 178453112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_partial_wipe 62243627716535649090945023150589386929187569525517913631966901880920300144933 117
UVM_INFO @ 7179572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed 1 test run
otbn_partial_wipe 112519982501895898165848752950282157627433552677943616181732614211626122254265 106
UVM_ERROR @ 8143898 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 8143898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_multi 41101877119979448300512358233553851637209681986714723977165279185111468312715 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 37300677062965707341564200895760670724346325935851567643287759134653120685305 320
UVM_INFO @ 1214692769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 14222772243075573349304228641028648079300918317413335209754644374772667820025 86
UVM_INFO @ 2522736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:507) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. 1 test run
otbn_escalate 4243803156987942948178189282816007230005541985047743261175438552042422683335 106
UVM_INFO @ 81403896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---