Simulation Results: rom_ctrl/32kb

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.82 %
  • code
  • 94.61 %
  • assert
  • 96.79 %
  • func
  • 99.06 %
  • block
  • 96.73 %
  • line
  • 97.22 %
  • branch
  • 94.09 %
  • toggle
  • 87.12 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.65%
V3
85.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 4.000s 137.770us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 7.000s 238.896us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 5.000s 128.313us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 6.000s 358.645us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 7.000s 133.100us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.000s 176.671us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 5.000s 128.313us 20 20 100.00
rom_ctrl_csr_aliasing 7.000s 133.100us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 5.000s 173.463us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 4.000s 171.520us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 5.000s 311.410us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 17.000s 762.599us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 7.000s 223.954us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 8.000s 206.501us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 8.000s 299.291us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 8.000s 299.291us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 7.000s 238.896us 5 5 100.00
rom_ctrl_csr_rw 5.000s 128.313us 20 20 100.00
rom_ctrl_csr_aliasing 7.000s 133.100us 5 5 100.00
rom_ctrl_same_csr_outstanding 5.000s 533.579us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 7.000s 238.896us 5 5 100.00
rom_ctrl_csr_rw 5.000s 128.313us 20 20 100.00
rom_ctrl_csr_aliasing 7.000s 133.100us 5 5 100.00
rom_ctrl_same_csr_outstanding 5.000s 533.579us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 68.000s 8427.478us 17 20 85.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 21.000s 3730.758us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 112.000s 1229.634us 5 5 100.00
rom_ctrl_tl_intg_err 31.000s 423.715us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 112.000s 1229.634us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 112.000s 1229.634us 5 5 100.00
sec_cm_checker_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 68.000s 8427.478us 17 20 85.00
sec_cm_checker_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 68.000s 8427.478us 17 20 85.00
sec_cm_checker_fsm_local_esc 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 68.000s 8427.478us 17 20 85.00
sec_cm_compare_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 68.000s 8427.478us 17 20 85.00
sec_cm_compare_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 68.000s 8427.478us 17 20 85.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 112.000s 1229.634us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 112.000s 1229.634us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 4.000s 137.770us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 4.000s 137.770us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 4.000s 137.770us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 31.000s 423.715us 20 20 100.00
sec_cm_bus_local_esc 19 22 86.36
rom_ctrl_corrupt_sig_fatal_chk 68.000s 8427.478us 17 20 85.00
rom_ctrl_kmac_err_chk 7.000s 223.954us 2 2 100.00
sec_cm_mux_mubi 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 68.000s 8427.478us 17 20 85.00
sec_cm_mux_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 68.000s 8427.478us 17 20 85.00
sec_cm_ctrl_redun 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 68.000s 8427.478us 17 20 85.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 21.000s 3730.758us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 112.000s 1229.634us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 17 20 85.00
rom_ctrl_stress_all_with_rand_reset 118.000s 4669.275us 17 20 85.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 3 test runs
rom_ctrl_stress_all_with_rand_reset 76246456838919957185609686758957915564201561465721660507723848663118924181769 94
UVM_INFO @ 678645585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 15719398384933839602172128576551281704684314996489139123630563328198933440022 90
UVM_INFO @ 316448670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 4270956878420042791926498574741021316999222095385150379500299199506008330937 90
UVM_INFO @ 660993603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 3 test runs
rom_ctrl_corrupt_sig_fatal_chk 78285541835226642314270085867149988298804180074632692955512810236058681238572 96
UVM_INFO @ 3915904702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 635708150133418575080612938087331040168491963626611068452028210210307917747 99
UVM_INFO @ 4151905095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 58661945884429195006264522909779407203456571265319205477439792807418848302753 93
UVM_INFO @ 1895472516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---