Simulation Results: rom_ctrl/64kb

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.90 %
  • code
  • 94.62 %
  • assert
  • 96.79 %
  • func
  • 99.29 %
  • block
  • 96.73 %
  • line
  • 97.22 %
  • branch
  • 94.09 %
  • toggle
  • 87.16 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 7.000s 420.571us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 11.000s 1063.820us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 7.000s 558.152us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 8.000s 655.645us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 7.000s 565.312us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 8.000s 1094.975us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 7.000s 558.152us 20 20 100.00
rom_ctrl_csr_aliasing 7.000s 565.312us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 8.000s 379.186us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 7.000s 1029.670us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 6.000s 2164.945us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 33.000s 4095.852us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 11.000s 1078.587us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 12.000s 3978.028us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 12.000s 1093.209us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 12.000s 1093.209us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 11.000s 1063.820us 5 5 100.00
rom_ctrl_csr_rw 7.000s 558.152us 20 20 100.00
rom_ctrl_csr_aliasing 7.000s 565.312us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.000s 298.856us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 11.000s 1063.820us 5 5 100.00
rom_ctrl_csr_rw 7.000s 558.152us 20 20 100.00
rom_ctrl_csr_aliasing 7.000s 565.312us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.000s 298.856us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 217.000s 31999.226us 20 20 100.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 40.000s 49626.464us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 221.000s 1498.859us 5 5 100.00
rom_ctrl_tl_intg_err 56.000s 5511.132us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 221.000s 1498.859us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 221.000s 1498.859us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 217.000s 31999.226us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 217.000s 31999.226us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 217.000s 31999.226us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 217.000s 31999.226us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 217.000s 31999.226us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 221.000s 1498.859us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 221.000s 1498.859us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 7.000s 420.571us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 7.000s 420.571us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 7.000s 420.571us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 56.000s 5511.132us 20 20 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 217.000s 31999.226us 20 20 100.00
rom_ctrl_kmac_err_chk 11.000s 1078.587us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 217.000s 31999.226us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 217.000s 31999.226us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 217.000s 31999.226us 20 20 100.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 40.000s 49626.464us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 221.000s 1498.859us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 18 20 90.00
rom_ctrl_stress_all_with_rand_reset 125.000s 20664.183us 18 20 90.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 2 test runs
rom_ctrl_stress_all_with_rand_reset 46565164983202347289610539247807326549088322773252650517580162228285294465700 93
UVM_INFO @ 431463644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 58091909451281721423796465520787142203349383646650118647930107663211576541380 93
UVM_INFO @ 865278978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---