Simulation Results: rstmgr

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.56 %
  • code
  • 99.59 %
  • assert
  • 97.62 %
  • func
  • 98.49 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.43 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
99.49%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 1.750s 71.564us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 1.450s 64.244us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 1.270s 36.745us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 4.170s 197.045us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 1.600s 40.436us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.950s 97.485us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 1.270s 36.745us 20 20 100.00
rstmgr_csr_aliasing 1.600s 40.436us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 2.270s 153.549us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 1.480s 47.470us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.430s 56.226us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 7.240s 831.998us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 7.240s 831.998us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 7.240s 831.998us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 7.240s 831.998us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 60.110s 7996.762us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.200s 37.359us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 2.730s 81.679us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 2.730s 81.679us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 1.450s 64.244us 5 5 100.00
rstmgr_csr_rw 1.270s 36.745us 20 20 100.00
rstmgr_csr_aliasing 1.600s 40.436us 5 5 100.00
rstmgr_same_csr_outstanding 1.570s 76.629us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 1.450s 64.244us 5 5 100.00
rstmgr_csr_rw 1.270s 36.745us 20 20 100.00
rstmgr_csr_aliasing 1.600s 40.436us 5 5 100.00
rstmgr_same_csr_outstanding 1.570s 76.629us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_sec_cm 34.630s 6876.090us 5 5 100.00
rstmgr_tl_intg_err 5.570s 624.682us 20 20 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 34.630s 6876.090us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 34.630s 6876.090us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 5.570s 624.682us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.840s 67.828us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 49 50 98.00
rstmgr_leaf_rst_cnsty 4.670s 448.793us 49 50 98.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 3.520s 291.532us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 34.630s 6876.090us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 1.270s 36.745us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 1.270s 36.745us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_cnsty_fault did not trigger max_delay:* 1 test run
rstmgr_leaf_rst_cnsty 91735640560292963656244280471159749000229438607925925886389571262391215882173 77
UVM_INFO @ 41941478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---