Simulation Results

Simulation Results: rv_dm/use_dmi_interface

16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
93.16 %

code
85.04 %

assert
96.43 %

func
98.00 %

block
94.35 %

line
94.84 %

branch
84.71 %

toggle
80.25 %

FSM
80.36 %

Validation stages

V1		98.89%
V2		54.42%
V2S		88.89%
V3		30.00%
unmapped		0.00%

178/180 passed

98.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	38.000s	3627.030us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	47.000s	789.318us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	51.000s	203.403us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	106.000s	40618.886us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	50.000s	392.640us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	61.000s	16293.048us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	68.000s	12469.298us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	142.000s	80969.521us	20	20	100.00
jtag_dmi_csr_aliasing				5	5	100.00
	rv_dm_jtag_dmi_csr_aliasing	84.000s	57610.800us	5	5	100.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	40.000s	220.919us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	40.000s	855.905us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	38.000s	714.847us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	44.000s	373.195us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	38.000s	721.056us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	48.000s	1653.993us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	40.000s	301.811us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	51.000s	368.266us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	40.000s	220.919us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	42.000s	381.338us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	44.000s	470.730us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	38.000s	714.847us	2	2	100.00
rom_read_access				2	2	100.00
	rv_dm_rom_read_access	36.000s	75.928us	2	2	100.00
csr_hw_reset				5	5	100.00
	rv_dm_csr_hw_reset	48.000s	842.046us	5	5	100.00
csr_rw				20	20	100.00
	rv_dm_csr_rw	47.000s	86.548us	20	20	100.00
csr_bit_bash				5	5	100.00
	rv_dm_csr_bit_bash	75.000s	1485.467us	5	5	100.00
csr_aliasing				5	5	100.00
	rv_dm_csr_aliasing	72.000s	51426.190us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	rv_dm_csr_mem_rw_with_rand_reset	50.000s	136.249us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	rv_dm_csr_aliasing	72.000s	51426.190us	5	5	100.00
	rv_dm_csr_rw	47.000s	86.548us	20	20	100.00
mem_walk				5	5	100.00
	rv_dm_mem_walk	46.000s	62.524us	5	5	100.00
mem_partial_access				5	5	100.00
	rv_dm_mem_partial_access	43.000s	87.921us	5	5	100.00

154/283 passed

54.42 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	38.000s	3627.030us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	46.000s	293.271us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	38.000s	312.911us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	35.000s	291.292us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	51.000s	474.615us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	57.000s	8510.184us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	50.000s	100.584us	0	20	0.00
bad_sba				0	20	0.00
	rv_dm_bad_sba_tl_access	53.000s	10739.233us	0	20	0.00
sba_autoincrement				4	20	20.00
	rv_dm_autoincr_sba_tl_access	91.000s	22699.061us	4	20	20.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	43.000s	148.348us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	43.000s	2069.989us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	48.000s	524.262us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	43.000s	38.776us	0	5	0.00
tap_ctrl_transitions				11	11	100.00
	rv_dm_tap_fsm	50.000s	8815.944us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	134.000s	5409.399us	10	10	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	33.000s	284.985us	1	1	100.00
stress_all				4	50	8.00
	rv_dm_stress_all	10802.145s	0.000us	4	50	8.00
alert_test				50	50	100.00
	rv_dm_alert_test	49.000s	88.353us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	rv_dm_tl_errors	54.000s	332.080us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	rv_dm_tl_errors	54.000s	332.080us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	rv_dm_csr_aliasing	72.000s	51426.190us	5	5	100.00
	rv_dm_csr_hw_reset	48.000s	842.046us	5	5	100.00
	rv_dm_csr_rw	47.000s	86.548us	20	20	100.00
	rv_dm_same_csr_outstanding	53.000s	887.943us	20	20	100.00
tl_d_partial_access				50	50	100.00
	rv_dm_csr_aliasing	72.000s	51426.190us	5	5	100.00
	rv_dm_csr_hw_reset	48.000s	842.046us	5	5	100.00
	rv_dm_csr_rw	47.000s	86.548us	20	20	100.00
	rv_dm_same_csr_outstanding	53.000s	887.943us	20	20	100.00

V2S

40/45 passed

88.89 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	rv_dm_sec_cm	43.000s	1761.742us	5	5	100.00
	rv_dm_tl_intg_err	64.000s	5847.143us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	rv_dm_tl_intg_err	64.000s	5847.143us	20	20	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				3	4	75.00
	rv_dm_sba_debug_disabled	43.000s	2069.989us	2	2	100.00
	rv_dm_debug_disabled	49.000s	36.732us	1	2	50.00
sec_cm_lc_dft_en_intersig_mubi				3	4	75.00
	rv_dm_sba_debug_disabled	43.000s	2069.989us	2	2	100.00
	rv_dm_debug_disabled	49.000s	36.732us	1	2	50.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	38.000s	3627.030us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				6	10	60.00
	rv_dm_buffered_enable	47.000s	89.453us	6	10	60.00
sec_cm_sba_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	50.000s	315.664us	4	4	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	50.000s	315.664us	4	4	100.00
sec_cm_exec_ctrl_mubi				6	10	60.00
	rv_dm_buffered_enable	47.000s	89.453us	6	10	60.00

3/10 passed

30.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				3	10	30.00
	rv_dm_stress_all_with_rand_reset	73.000s	2903.911us	3	10	30.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	426.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				40 test runs
	rv_dm_sba_tl_access	67485244330129473853812539091123101997314540145503174953619167061062985422465	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24229
	rv_dm_bad_sba_tl_access	9742696737480107658284269912439326145269246265171407585574597617858384942399	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10051
	rv_dm_sba_tl_access	517105329099156254701628723112987401603597742593991988669583117872938720010	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10291
	rv_dm_bad_sba_tl_access	16311657311450344637908853269835509273053514984700357151351891290347284385454	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10291
	rv_dm_autoincr_sba_tl_access	33753622036872552556889196764261477905096375905478152091660880356811638115185	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24990
	rv_dm_sba_tl_access	23230009358778111984263761091808694125700584811570593872075479606069231561606	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24264
	rv_dm_bad_sba_tl_access	6643895988445044476583349453283802582571963202799557709420131094136780456065	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10081
	rv_dm_sba_tl_access	21733176166289656706300257208215435509805340097546971951553540903681169483031	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24195
	rv_dm_bad_sba_tl_access	59460159261933030456530279090286262421379149970377630120687745182712880929350	93	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24236
	rv_dm_sba_tl_access	49679643704999307081107435798129178197678235536467381622681632422697357830049	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24245
	rv_dm_sba_tl_access	51086805767006350474075224639697727435193506951586888152601917712822229158867	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24199
	rv_dm_sba_tl_access	81058586782295322657737474875073767311215485011505996321647814533154360948408	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24205
	rv_dm_bad_sba_tl_access	1695681946008362112139501318001884831293091344929805085872722217897352338632	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24318
	rv_dm_sba_tl_access	46586717661521092252272759788777792549804221146829884135484140716463865221451	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24187
	rv_dm_bad_sba_tl_access	46298132441507908046731660187142088339190875419648473137535194019756352903362	114	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24258
	rv_dm_autoincr_sba_tl_access	109935815177677514809174120732109922837718629109542143508013327909220328090479	126	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24305
	rv_dm_sba_tl_access	47165908937564282682425320143625950879925750131770724005366880076269804543599	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24194
	rv_dm_sba_tl_access	95804388738217060236958699617098158066924209229689947181534838819267451272987	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24244
	rv_dm_sba_tl_access	114142070875830270030237680419208962095899363574215928252030291024479102557240	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24256
	rv_dm_bad_sba_tl_access	83210126846904147564353426199318019249017109923289921886463000059071100702721	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24208
	rv_dm_sba_tl_access	16203225605022223681828489026404848207759856469562464803775177108325380468623	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24199
	rv_dm_bad_sba_tl_access	111816627040044487699182505217337268276573889917607504984787749984451460317260	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24206
	rv_dm_autoincr_sba_tl_access	99289408674422097776995775466744127025596074450771659372202839791730208298668	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24291
	rv_dm_sba_tl_access	63546436019193625038325171077979390520721422554705711593290693082666903714905	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24249
	rv_dm_bad_sba_tl_access	95480539372571410969212755230431755429303559724644485652572747561574398172831	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10291
	rv_dm_sba_tl_access	85369912327045758412488413856972636975299887534547219626403163687881217486118	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24171
	rv_dm_bad_sba_tl_access	16538670763036808060892332934862936184272934019206303023830953168960373480745	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24123
	rv_dm_sba_tl_access	23693448962328079067533293378299421592000601860969470540606914112165821348812	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24231
	rv_dm_bad_sba_tl_access	114944885802614569749142121960756357899827199265453628415599906306692633423811	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24267
	rv_dm_autoincr_sba_tl_access	35167441606404822402043309046941251671609682479037400271984294593688090012664	132	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @26368
	rv_dm_sba_tl_access	31067599864600090016799324034086183420693555077809842411143042220801637476618	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24167
	rv_dm_bad_sba_tl_access	34727739015051459383795208964385090090145373771657742572224342309860760929946	114	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24332
	rv_dm_sba_tl_access	49834671049711150596843812482790101663495187762544808823243949770454179475173	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24185
	rv_dm_autoincr_sba_tl_access	90950725456812732957992352307754092037618060368459521416386024898957051738048	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24169
	rv_dm_sba_tl_access	65229469437558317928247842811020450916835788031918009139065671196907349685978	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24268
	rv_dm_autoincr_sba_tl_access	67487633039999363680058438592940746441290112561658405397797163506282198089276	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24341
	rv_dm_sba_tl_access	42821610753250045738241243938977577827134093569851501730094902564190074778976	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24204
	rv_dm_sba_tl_access	34709925147639932460018017705627939852675578614383420085402876251474857490606	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24250
	rv_dm_bad_sba_tl_access	42740686020827106299136037548061000241537515466673287675801891581447753010906	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24118
	rv_dm_autoincr_sba_tl_access	101443514706332171042300081533837481504737230136899959480834739361399095995950	144	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24368
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				36 test runs
	rv_dm_delayed_resp_sba_tl_access	91378447454452395086802340827514601892632639743241808963250033621280406113532	107	UVM_INFO @ 150644731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	77809052806559727112344478197691468693562637630657342194085998449754615733656	107	UVM_INFO @ 135056187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	9877571592740151147037073918834402747747181759442881157918027187242643300832	107	UVM_INFO @ 768715441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	73204791790252571495807969752952129586742848990902792528657804591504886154470	107	UVM_INFO @ 361585524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	91189776877409865566444937460165276078466068417632171251440963971001327774288	107	UVM_INFO @ 55399163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	51320495276008247268249585140932088511122374746355931554582630365344142077147	107	UVM_INFO @ 217121440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	57492063159636885997390814439801048309567202550685266225143868382529370606192	107	UVM_INFO @ 312707443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	106243088431456666273922608163609552805765103442182101494438710143159713195369	107	UVM_INFO @ 197505676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	16148879500086332311404834325591661527054424950573668647990846705705963501837	107	UVM_INFO @ 96224154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	105534672117417619590278356186967854607357006912503569933294686415365417650262	107	UVM_INFO @ 100583625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	16085716134191542391044594538500411553601660430520019602407916943253928349849	107	UVM_INFO @ 88629588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	40453298722370492879547315551657845701742189736566914752586398997273252798614	107	UVM_INFO @ 863976858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	10057436794259769884833493085692392354815985954831269588109594523514198101844	107	UVM_INFO @ 252848909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	15154701010792856977175832808527929201005262452853785676120741806084053022374	107	UVM_INFO @ 1096819591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	73897690223307735923559796782101697910752648136300601832472764854749845543951	107	UVM_INFO @ 71320579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	90059661286014739860565405019731833509788691344173711906691784654127787513731	107	UVM_INFO @ 134229325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	76830138525838100132773758115094570287764232419497028991726227825250385782243	107	UVM_INFO @ 468027414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	105586825604144598075430590295877802061292633809702321134560102859606945447182	107	UVM_INFO @ 269401504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	6754681258501715097065724427233028031890920419576238823182022172047105833811	107	UVM_INFO @ 52314066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	11272061349561617355431749515237975538140859874040200253041225274138878808511	107	UVM_INFO @ 126924541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	24658630951958225010129675428061944268707823881336360605668309197975170235557	107	UVM_INFO @ 266521773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	15392447935919498673060978740934813479352633673555111843057435273799332609483	107	UVM_INFO @ 70341051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	47672345321848851353050298936125076789614928221736050731606392167608930384053	107	UVM_INFO @ 426109838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	43454427842298096378531253321183089974752075626636575142305023235325628071337	107	UVM_INFO @ 127902237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	65793699359373057628030172188948437392353020206485230074558596994055237641832	107	UVM_INFO @ 167579826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	19481853378694426942575002161425310941442868947305412841618203966783162807774	107	UVM_INFO @ 110489292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	55682626002919899219016419275279692364190968429515925151277313836798851981357	107	UVM_INFO @ 311685389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	22214811781872958315914705151267401812958061632645010310449131325972997149303	107	UVM_INFO @ 336288246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	53228728641606756003558352345728445666100040238389041654662643729025557806419	107	UVM_INFO @ 52550199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	72253598761586717537093415389013594266574283025132014462396897203268193051991	107	UVM_INFO @ 55015608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	102126827548798624040152465083857746452344569704871316377714303845714241530084	107	UVM_INFO @ 364525000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	61556244346664213925114375294842420788782456385193419035856831905348086480386	107	UVM_INFO @ 386618328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	23688515963110593775581656581351136468091461672421458593493806450267885760961	107	UVM_INFO @ 152910915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	79665925876315873320595946224814953573952016622082654399672240832602054617930	107	UVM_INFO @ 360341971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	110485369523291538393134356500647622299108870512151535859927714768451611757829	107	UVM_INFO @ 188142234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	57322629200450759993062047785391720395188996188855602326574557036110179527346	107	UVM_INFO @ 392622547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				19 test runs
	rv_dm_mem_tl_access_resuming	62987760081794939369528921431116898808105450155463180823779806636797081527338	87	UVM_INFO @ 373195073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	43892025910471262007596925658663590249242481816453821040408730583574557779591	92	UVM_INFO @ 3117362394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	42000430504998381453736500065607387769970240248932558129238530786065382118498	87	UVM_INFO @ 583727738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	94161192393962390618282429631100135733151866473333406836970328259428760492133	88	UVM_INFO @ 282903000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	113274586556836288518592611923102079289536267736923022445521547480797194631384	99	UVM_INFO @ 530713635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	42967801204234705539785237149998785965249739658279477444856262832453132505638	108	UVM_INFO @ 1202672405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	41934096548564538568166958110538040446825731472982250687307642948006962527481	89	UVM_INFO @ 197738824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	7579497753123766740527177807458101092071966676950232012403396626420812476773	89	UVM_INFO @ 693840413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	37469330958956134453912181372416194952112788880931107620048747872074949637371	88	UVM_INFO @ 545987563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	16099125710545197629903474271963370656158130293004021543030345511766788207460	95	UVM_INFO @ 7441801206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	83466790016593518863914735603461606165082799718719907342552447430889303568883	92	UVM_INFO @ 1377334102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	62253483462641162560504965840741117549174332541971557368961392072098678889764	93	UVM_INFO @ 3211854485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	69187808388336516598636484044350410541963263922282174102969368953164990695185	91	UVM_INFO @ 913803461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	98255432610472292998768816381636279806201219803457638955065044698400244386409	89	UVM_INFO @ 349095446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	6358282437832067099788047476781259641523823820255890482335446457759560500519	89	UVM_INFO @ 663000079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	3590782055358294472099069867425981216274907017603590030257108908825099833347	92	UVM_INFO @ 1115824269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	93143039081431202204840468233808180181502128037438580039583144312677094940730	108	UVM_INFO @ 3116828935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	10753071875885172299357805578782998431149704009338423779118932227724455658638	88	UVM_INFO @ 691677093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	43472813656882169608411590348301158675966348114546770348056397060455270377304	89	UVM_INFO @ 1326959125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				18 test runs
	rv_dm_hart_unavail	61777258690946760862040081206735250237694302714969032872181207530465174499675	87	UVM_INFO @ 76549755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	13670892285331261709954107228798239061399323408489975297264685422535326876050	87	UVM_INFO @ 121718743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	36504003511132422495671444868950828068640801300903483860421910148901646833899	93	UVM_INFO @ 1260770557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	101911133981884510465922500702952260788069197754590592243654711622501975968552	87	UVM_INFO @ 33783209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	23261249393065643942012227885247109983401412511124893098300987385765169406318	87	UVM_INFO @ 53831847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	57337577209818077184335170904567859651658982912892988069362465611929233842491	87	UVM_INFO @ 38776031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	15509389445059880133222380481787739336962985599561481823633450152924018353132	88	UVM_INFO @ 104943185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	80698782275815902464120613976021965518831567233668610521089178563207871014433	89	UVM_INFO @ 1096107613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	66513317187041388665094749546576545141657213204077188377542768006791306438112	89	UVM_INFO @ 699705850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	24862583029140497673420902055396531049324651398291431711682191436276351641701	90	UVM_INFO @ 2273191872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	36058323339326670073284870091707292554063761513976105357572211266325462203658	88	UVM_INFO @ 127345605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	56887797242877889024290093342028291982321960481529669364691339414074749107978	89	UVM_INFO @ 214829195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	86629506820271146263051174584514507061793032941060307828802584487076911043344	92	UVM_INFO @ 1937918720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	35293487488678220260969251705977159398834361538559920810617647534260360560910	93	UVM_INFO @ 2105323300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	75828593262853637065593801699652060748522777441675148781956563193431286732919	88	UVM_INFO @ 316601277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	33449578243921826619955719401601616535388602828140258468751052333515728121182	89	UVM_INFO @ 938758658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	43046963859004232679821871595913681794891642304543988994480753224304839247297	91	UVM_INFO @ 3080685818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	41734353966377080247162168683585645611856689024275327050471553531017113177959	90	UVM_INFO @ 1033109562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				13 test runs
	rv_dm_jtag_dmi_debug_disabled	81812835168363092086558903177840867825608261318285322826988359914991434964223	87	UVM_INFO @ 148348435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	84072082276782942355723907938815981797483699313339572685943857882642935723721	87	UVM_INFO @ 112732896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	3036970768371051200380930313549434475073434546947908017176935109435044978916	88	UVM_INFO @ 511991858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	68530061235727859429323631688134811640519089947802390020368979121698502830607	114	UVM_INFO @ 2224307192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	23424143624307574557605131561099392131698086942505680859424728140224041963141	88	UVM_INFO @ 149282277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	8729129207218379368864853854832548870575101124693296966051675675007738877623	103	UVM_INFO @ 852258940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	73244713068762884177279590550278367756061584779876896144112883007016230537348	88	UVM_INFO @ 174843345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	97874045822452514141771703956549395789049932814268809686946703520324061917303	93	UVM_INFO @ 4367056176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	82674375023303282040387694752388676184380690986928511203576240708195876615	88	UVM_INFO @ 142978787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	1167191624605612831454453135883062033109967254744838949370346803957342305619	92	UVM_INFO @ 2090557361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	91060030095443688796132901721886000150293597792295438474636238341719524872478	89	UVM_INFO @ 358561604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	72498857030213648031526957417911444454005486106800549572972841283299698509484	92	UVM_INFO @ 2943199494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	106782474150369124424314545648892773267252784306987748904087948117544568845877	88	UVM_INFO @ 118799380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				6 test runs
	rv_dm_stress_all	111844750767861691606032099569390095506940838067258221560945826493760133394742	None
	rv_dm_stress_all	97945324981582109727209935539520974061348365461539404612724608660586255682035	None
	rv_dm_stress_all	21039306948484027146915959809482399051635742044876909422627398748058970059178	None
	rv_dm_stress_all	9804614907505509872949870419143529046044434273418101216487501671681725210253	None
	rv_dm_stress_all	98076239731433115047322607579931024891115075638801685154352692553007053243692	None
	rv_dm_stress_all	86043197298049800804918005322941103018232040354422839137422385276966992891920	None
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				4 test runs
	rv_dm_scanmode	38640681201688399790738055216553980821634246135592240419226231700816804855277	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	46424469173188854515053625627549992971579979698782575008539967379409211577737	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	22907518929692103344462118568178740780495271626036977554099599006037722256078	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	80106584234122691350910414117814880407135836673431126992201655972359768127954	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])				4 test runs
	rv_dm_buffered_enable	40876972633715148467142766806948534918328455306098270984170538513497133460376	91	UVM_INFO @ 91479963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	4449455372710258395534574920159105546440523373836689954003766812009793054629	89	UVM_INFO @ 281768418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	89072268069615866019458388291756750385574326931645103427628954189612086492002	92	UVM_INFO @ 128380260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	92573590375713898621176118781934843233878008569933223462044524966678175600248	90	UVM_INFO @ 83856283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_dm_common_vseq] Check failed (vseq_done)				3 test runs
	rv_dm_stress_all_with_rand_reset	109863365227039922291649106701109974040398307851439050952990852538311889875893	110	UVM_INFO @ 1295491873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	57733918541286161612478077982124604109229577072531236093478805495959860973635	99	UVM_INFO @ 4292979538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	44888781146456225464109509877972677303860440020428304595749385249083370416773	114	UVM_INFO @ 1507687525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_debug_disabled_vseq.sv:33) [rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output)				1 test run
	rv_dm_debug_disabled	92127816371486328169489459486023942668231075748611000415145488806354190127184	89	UVM_INFO @ 36731957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---