Simulation Results: rv_timer

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.46 %
  • code
  • 95.85 %
  • assert
  • 96.52 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
98.67%
V2
92.92%
V2S
100.00%
V3
45.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 3.000s 214.243us 20 20 100.00
csr_hw_reset 5 5 100.00
rv_timer_csr_hw_reset 2.000s 59.514us 5 5 100.00
csr_rw 20 20 100.00
rv_timer_csr_rw 1.000s 15.252us 20 20 100.00
csr_bit_bash 5 5 100.00
rv_timer_csr_bit_bash 4.000s 557.094us 5 5 100.00
csr_aliasing 5 5 100.00
rv_timer_csr_aliasing 2.000s 103.041us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
rv_timer_csr_mem_rw_with_rand_reset 4.000s 10086.188us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rv_timer_csr_rw 1.000s 15.252us 20 20 100.00
rv_timer_csr_aliasing 2.000s 103.041us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 3 20 15.00
rv_timer_random_reset 12.000s 10310.372us 3 20 15.00
disabled 20 20 100.00
rv_timer_disabled 5.000s 2721.175us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 771.000s 522585.490us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 771.000s 522585.490us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 9.000s 12156.125us 20 20 100.00
alert_test 50 50 100.00
rv_timer_alert_test 2.000s 14.348us 50 50 100.00
intr_test 50 50 100.00
rv_timer_intr_test 2.000s 12.132us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rv_timer_tl_errors 3.000s 158.624us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rv_timer_tl_errors 3.000s 158.624us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rv_timer_csr_hw_reset 2.000s 59.514us 5 5 100.00
rv_timer_csr_rw 1.000s 15.252us 20 20 100.00
rv_timer_csr_aliasing 2.000s 103.041us 5 5 100.00
rv_timer_same_csr_outstanding 2.000s 138.435us 20 20 100.00
tl_d_partial_access 50 50 100.00
rv_timer_csr_hw_reset 2.000s 59.514us 5 5 100.00
rv_timer_csr_rw 1.000s 15.252us 20 20 100.00
rv_timer_csr_aliasing 2.000s 103.041us 5 5 100.00
rv_timer_same_csr_outstanding 2.000s 138.435us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rv_timer_sec_cm 1.000s 381.130us 5 5 100.00
rv_timer_tl_intg_err 3.000s 298.019us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
rv_timer_tl_intg_err 3.000s 298.019us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 2 10 20.00
rv_timer_min 2.000s 981.046us 2 10 20.00
max_value 1 10 10.00
rv_timer_max 2.000s 469.491us 1 10 10.00
stress_all_with_rand_reset 15 20 75.00
rv_timer_stress_all_with_rand_reset 48.000s 5883.927us 15 20 75.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 25 test runs
rv_timer_min 76058548010364170463675505198267910938078927653186145625123208807278576517841 86
UVM_INFO @ 981046377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 50695681944466594277495673216508977110555818634843091811327632781082558449067 84
UVM_INFO @ 250286973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 5405991299691606998420481148326561139668597643891339078051179531225327572722 87
UVM_INFO @ 197744531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 92111053822268884415781305616506260635738308655422912424018247450309369711226 85
UVM_INFO @ 215856360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 42626513441802963666944937957847000439662918897005028246199406584866790061065 85
UVM_INFO @ 118026889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 84751471509310275006247570232344087485155101207512479416981561129568011142735 85
UVM_INFO @ 85618871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 76143095751264249476271048937428623919160606704231959178154504426599930964307 84
UVM_INFO @ 729193111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 101420578629330801896859273425249127906149885794741962531896658982010216791070 84
UVM_INFO @ 74829227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 19496362157023868519609176284143581103822723280994066805477015353781405966878 84
UVM_INFO @ 122407147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 27950315170336433962351227298745988902010219973672436676648426365142223173122 85
UVM_INFO @ 55680705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 16653345073714530801463423782817747413515057924594294996645312524324519964472 84
UVM_INFO @ 383405709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 64311423083871444215570739958809474179414399778533717357460418124063080826645 84
UVM_INFO @ 219176424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 83333070041782485587571474266046247791125905576319754210370504549557584069056 84
UVM_INFO @ 390776628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 37173537477471514997286258797268727431083128789066812278528623139643102674979 86
UVM_INFO @ 109865914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 83242765766605442873204800041434186299407333879888131808458965008606220096119 84
UVM_INFO @ 329637236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 103901429148987243748067013556022208779231547108475747215051381545206223555110 85
UVM_INFO @ 1099416881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 115069518068593685249596240115663011415060888321082874221226818990111365175578 84
UVM_INFO @ 312445223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 90462458463102946900085743587796317745755698028429972465979964318439627360015 84
UVM_INFO @ 775195156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 98818108889570424069627895796360664858944652661931163977129823794277753808429 84
UVM_INFO @ 205621427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 46872647315991491044379636694471007333731646413119368372554467707584425614042 84
UVM_INFO @ 68928542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 49206148997726583845346675662880541989822826953960797075384074619889555202483 85
UVM_INFO @ 10310372134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 63552245240152134404674573838179300487101205337336288228097268496448026306689 84
UVM_INFO @ 1019323287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 65870167440368603544376719906398849038991833052979569627633104652184585146067 85
UVM_INFO @ 368218626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 98853850248801827714080401664006075561072885395945536354900857536293839113168 85
UVM_INFO @ 139817136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 61662582403318102985610647867597923092339066753870703583524215881347592707284 84
UVM_INFO @ 209598342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 9 test runs
rv_timer_max 29023922082190247621851938721200546692788373405413368329855205676864718597123 85
UVM_INFO @ 469490988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 95858368802142850695242688870578302203990478286891424099618169032396893177110 84
UVM_INFO @ 48654743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 4728587014468265183233372342295557998618709454223332777815534882196169229472 86
UVM_INFO @ 88788284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 89935710264833904134126704304861974243394993038857017003453048512935542723626 86
UVM_INFO @ 65896376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 88636663771737447402373294766799965302591494683309793600097636787634506708577 84
UVM_INFO @ 91197124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 106702387564542968948942142245136024024215819463479730347515611327523238588436 85
UVM_INFO @ 174941347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 70227337230496535114609053473781081915517373084564095115711871554820498012104 84
UVM_INFO @ 531492447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 38540379792909310498349425912368591564749406302954282757674087993126524289033 84
UVM_INFO @ 42408565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 22860099369234812923311834348437011638146032021988643228371987598401684268756 86
UVM_INFO @ 168843579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) 3 test runs
rv_timer_stress_all_with_rand_reset 13231368602742855478969170177338051703560776634350314125252770472812887042349 162
UVM_INFO @ 233994502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 70051682889770343860149012436409560804997727726631238649651622753606454805774 177
UVM_INFO @ 14309767087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 32922802338576629901576856540049488359850830357311253789154603895802362902947 173
UVM_INFO @ 20846739867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
rv_timer_stress_all_with_rand_reset 97167556318252093362799800803221388613811622075407757166689195691442231461101 187
UVM_INFO @ 8895121781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 108401849250916360653243494672685173980947795278561075148843549698319982172973 101
UVM_INFO @ 26881271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [rv_timer_common_vseq] wait timeout occurred! 1 test run
rv_timer_csr_mem_rw_with_rand_reset 98632834935921903548968305485156162673678309238538743071025829144427155296573 101
UVM_INFO @ 10086188156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---