Simulation Results: spi_host

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.81 %
  • code
  • 95.03 %
  • assert
  • 95.64 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
99.13%
V2
99.09%
V2S
100.00%
unmapped
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 49 50 98.00
spi_host_smoke 111.000s 10325.882us 49 50 98.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 2.000s 25.619us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 2.000s 71.632us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 4.000s 165.681us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 2.000s 60.051us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 117.048us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 2.000s 71.632us 20 20 100.00
spi_host_csr_aliasing 2.000s 60.051us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 2.000s 96.052us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 1.000s 116.442us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 3.000s 181.973us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 38.000s 1864.412us 50 50 100.00
spi_host_error_cmd 2.000s 67.100us 50 50 100.00
spi_host_event 639.000s 21186.142us 50 50 100.00
clock_rate 48 50 96.00
spi_host_speed 132.000s 200000.000us 48 50 96.00
speed 48 50 96.00
spi_host_speed 132.000s 200000.000us 48 50 96.00
chip_select_timing 48 50 96.00
spi_host_speed 132.000s 200000.000us 48 50 96.00
sw_reset 49 50 98.00
spi_host_sw_reset 296.000s 10012.326us 49 50 98.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 2.000s 81.067us 50 50 100.00
cpol_cpha 48 50 96.00
spi_host_speed 132.000s 200000.000us 48 50 96.00
full_cycle 48 50 96.00
spi_host_speed 132.000s 200000.000us 48 50 96.00
duplex 49 50 98.00
spi_host_smoke 111.000s 10325.882us 49 50 98.00
tx_rx_only 49 50 98.00
spi_host_smoke 111.000s 10325.882us 49 50 98.00
stress_all 48 50 96.00
spi_host_stress_all 2070.000s 1000000.000us 48 50 96.00
spien 50 50 100.00
spi_host_spien 156.000s 30987.848us 50 50 100.00
stall 49 50 98.00
spi_host_status_stall 174.000s 87544.413us 49 50 98.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 40.000s 8362.160us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 38.000s 1864.412us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 2.000s 60.633us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 2.000s 57.424us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 3.000s 178.879us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 3.000s 178.879us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 25.619us 5 5 100.00
spi_host_csr_rw 2.000s 71.632us 20 20 100.00
spi_host_csr_aliasing 2.000s 60.051us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 18.379us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 25.619us 5 5 100.00
spi_host_csr_rw 2.000s 71.632us 20 20 100.00
spi_host_csr_aliasing 2.000s 60.051us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 18.379us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_tl_intg_err 3.000s 101.932us 20 20 100.00
spi_host_sec_cm 2.000s 135.805us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 3.000s 101.932us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 8 10 80.00
spi_host_upper_range_clkdiv 810.000s 50025.978us 8 10 80.00

Error Messages

   Test seed line log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* 3 test runs
spi_host_smoke 103206355436105935711174709603106615777801320677592240782361129740538997916426 164
UVM_INFO @ 15023715160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_upper_range_clkdiv 9098798317753715937728269342457535007357120248779631329030467978214184060593 173
UVM_INFO @ 50025978063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_upper_range_clkdiv 67483748726977332743516437178201286187244163588044539248101540235001467076702 158
UVM_INFO @ 100061202968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 3 test runs
spi_host_stress_all 96468364711033123853551156424691874607561373244236833403364761971800360118110 372
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_stress_all 29574597127285771443748866067095669403570799703971843730505806282588657053894 380
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_speed 32516566867653490114201492255568464686073433988910658159828661213701092716982 149
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed 1 test run
spi_host_status_stall 61954420968468068521590265233454524337528091504763091924697166724206540688508 1308
UVM_ERROR @ 1381092396 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=1381092000 ps
UVM_INFO @ 1381092396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* 1 test run
spi_host_speed 89755889962465886801311018702793640536691800687653175256583340675360461949553 343
UVM_INFO @ 10048024885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* 1 test run
spi_host_sw_reset 38866401030417497971977688400877182556280187276096038573224552963095552154021 274
UVM_INFO @ 10012326303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---