Simulation Results: sram_ctrl/main

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.59 %
  • code
  • 96.90 %
  • assert
  • 96.46 %
  • func
  • 96.40 %
  • block
  • 96.28 %
  • line
  • 97.03 %
  • branch
  • 94.49 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 7.000s 2743.685us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 2.000s 14.068us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 16.239us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 4.000s 845.509us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 16.426us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 5.000s 6840.525us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 16.239us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 16.426us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 273.000s 42233.104us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 112.000s 22287.243us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 38.000s 6506.674us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 201.000s 40071.131us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 165.000s 37959.661us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 83.000s 96817.207us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 61.000s 35813.359us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 39.000s 32101.930us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 7.000s 4097.172us 5 5 100.00
sram_ctrl_partial_access_b2b 382.000s 48232.019us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 7.000s 2896.651us 5 5 100.00
sram_ctrl_throughput_w_partial_write 8.000s 699.619us 5 5 100.00
sram_ctrl_throughput_w_readback 7.000s 2790.343us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 21.000s 5173.510us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 5.000s 1410.541us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 404.000s 21139.589us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 18.450us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 2072.513us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 2072.513us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 14.068us 5 5 100.00
sram_ctrl_csr_rw 2.000s 16.239us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 16.426us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 51.297us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 14.068us 5 5 100.00
sram_ctrl_csr_rw 2.000s 16.239us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 16.426us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 51.297us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 43.000s 28220.172us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_sec_cm 5.000s 2307.725us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 3100.300us 20 20 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 2307.725us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.000s 3100.300us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 21.000s 5173.510us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 21.000s 5173.510us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 16.239us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 39.000s 32101.930us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 39.000s 32101.930us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 39.000s 32101.930us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 61.000s 35813.359us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 9.000s 2798.582us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 43.000s 28220.172us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 7.000s 698.711us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 7.000s 2743.685us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 7.000s 2743.685us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 39.000s 32101.930us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 2307.725us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 61.000s 35813.359us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 2307.725us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 2307.725us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 7.000s 2743.685us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 2307.725us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 31.000s 1191.091us 5 5 100.00