Simulation Results: sram_ctrl/ret

 
16/05/2026 03:01:19 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.15 %
  • code
  • 83.42 %
  • assert
  • 96.43 %
  • func
  • 96.60 %
  • block
  • 93.87 %
  • line
  • 95.04 %
  • branch
  • 89.67 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
97.14%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 2.000s 481.338us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 1.000s 34.723us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 39.936us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 4.000s 1195.394us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 64.671us 5 5 100.00
csr_mem_rw_with_rand_reset 18 20 90.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 58.485us 18 20 90.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 39.936us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 64.671us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 12.000s 443.391us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 4.000s 209.179us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 12.000s 539.036us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 198.000s 28645.188us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 8.000s 650.514us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 27.000s 3063.273us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 7.000s 1048.869us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 12.000s 1876.100us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 2.000s 41.263us 5 5 100.00
sram_ctrl_partial_access_b2b 290.000s 18399.012us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 2.000s 42.140us 5 5 100.00
sram_ctrl_throughput_w_partial_write 2.000s 117.554us 5 5 100.00
sram_ctrl_throughput_w_readback 3.000s 42.845us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 9.000s 573.731us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 2.000s 125.602us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 57.000s 7519.610us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 44.194us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 5.000s 69.158us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 5.000s 69.158us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.000s 34.723us 5 5 100.00
sram_ctrl_csr_rw 2.000s 39.936us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 64.671us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 19.618us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 1.000s 34.723us 5 5 100.00
sram_ctrl_csr_rw 2.000s 39.936us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 64.671us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 19.618us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 3463.572us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_sec_cm 8.000s 1280.375us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 1332.070us 20 20 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 8.000s 1280.375us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.000s 1332.070us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 9.000s 573.731us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 9.000s 573.731us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 39.936us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 12.000s 1876.100us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 12.000s 1876.100us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 12.000s 1876.100us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 7.000s 1048.869us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 2.000s 237.332us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 3463.572us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 2.000s 133.794us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 2.000s 481.338us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 2.000s 481.338us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 12.000s 1876.100us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 8.000s 1280.375us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 7.000s 1048.869us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 8.000s 1280.375us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 8.000s 1280.375us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 2.000s 481.338us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 8.000s 1280.375us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 85.000s 5540.171us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * 2 test runs
sram_ctrl_csr_mem_rw_with_rand_reset 100728648104989442004433441998531369671381413091074865276976776691137770533059 88
UVM_INFO @ 46968575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_csr_mem_rw_with_rand_reset 68659730070722218225661433633349262129114017486512329974337906604020557291010 94
UVM_INFO @ 87602764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---