Simulation Results: ac_range_check

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.32 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.67 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
96.84%
V2
96.27%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 19 20 95.00
ac_range_check_smoke 59.000s 1725.205us 19 20 95.00
ac_range_check_smoke_racl 18 20 90.00
ac_range_check_smoke_racl 64.000s 5822.549us 18 20 90.00
csr_hw_reset 5 5 100.00
ac_range_check_csr_hw_reset 9.000s 166.878us 5 5 100.00
csr_rw 20 20 100.00
ac_range_check_csr_rw 6.000s 37.806us 20 20 100.00
csr_bit_bash 5 5 100.00
ac_range_check_csr_bit_bash 47.000s 2915.481us 5 5 100.00
csr_aliasing 5 5 100.00
ac_range_check_csr_aliasing 36.000s 1439.448us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
ac_range_check_csr_mem_rw_with_rand_reset 6.000s 26.728us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
ac_range_check_csr_rw 6.000s 37.806us 20 20 100.00
ac_range_check_csr_aliasing 36.000s 1439.448us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 249.516us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 45.000s 479.831us 1 1 100.00
stress_all 41 50 82.00
ac_range_check_stress_all 281.000s 9341.368us 41 50 82.00
alert_test 50 50 100.00
ac_range_check_alert_test 22.000s 15.083us 50 50 100.00
intr_test 50 50 100.00
ac_range_check_intr_test 2.000s 15.070us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
ac_range_check_tl_errors 6.000s 1042.661us 20 20 100.00
tl_d_illegal_access 20 20 100.00
ac_range_check_tl_errors 6.000s 1042.661us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
ac_range_check_csr_hw_reset 9.000s 166.878us 5 5 100.00
ac_range_check_csr_rw 6.000s 37.806us 20 20 100.00
ac_range_check_csr_aliasing 36.000s 1439.448us 5 5 100.00
ac_range_check_same_csr_outstanding 7.000s 1171.800us 20 20 100.00
tl_d_partial_access 50 50 100.00
ac_range_check_csr_hw_reset 9.000s 166.878us 5 5 100.00
ac_range_check_csr_rw 6.000s 37.806us 20 20 100.00
ac_range_check_csr_aliasing 36.000s 1439.448us 5 5 100.00
ac_range_check_same_csr_outstanding 7.000s 1171.800us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 24.000s 1183.338us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 24.000s 1183.338us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 24.000s 1183.338us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 24.000s 1183.338us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 108.000s 4924.001us 20 20 100.00
tl_intg_err 25 25 100.00
ac_range_check_sec_cm 2.000s 13.246us 5 5 100.00
ac_range_check_tl_intg_err 13.000s 1982.185us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
ac_range_check_stress_all_with_rand_reset 377.000s 4109.709us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 42.000s 1313.379us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 11 test runs
ac_range_check_stress_all 23343016243564907689228049326408759208782142780120612823631950019214366869405 13787
UVM_INFO @ 43960574060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 27141662413010183162014612329992971590185642929907464649342942014579685527190 9764
UVM_INFO @ 55142166435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke 86321165716309505470444691924641166971856582730801541557346742353311507069302 4596
UVM_INFO @ 3159039592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 80153490617287471487338166063163392443285579367167891211819938168934224917746 22447
UVM_INFO @ 9769310237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 73475363004276671965522142506669523518933720784133107147338401270926922202366 4012
UVM_INFO @ 7525277017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 62983063406132045314096868765166759697489798435630367130098205686076704743501 4078
UVM_INFO @ 5822548854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 29268802078980134136848658353415739102127589317196474518839599599417431635281 9550
UVM_INFO @ 3096449484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 75220476561906531318894966410910511805771003302609865509296945228871770673982 18034
UVM_INFO @ 1972536478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 39845147177870998693000017300761743900706734673736020292769547761848045157725 8232
UVM_INFO @ 3485256284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 28122943005359337375311301001135070701893295660580949136852192134220908445989 18198
UVM_INFO @ 4221206134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 100651466755656419057779395764475850463602717105040835721797013279836676752029 4103
UVM_INFO @ 9576198694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (ac_range_check_scoreboard.sv:166) [scoreboard] Unable to get any item from tl_unfilt_d_chan_fifo. 1 test run
ac_range_check_stress_all 104814398636506959579092586822454380049663997128934069935048215615408536119729 10787
UVM_INFO @ 100525158092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---