Simulation Results: aes/gcm_unmasked

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.86 %
  • code
  • 94.33 %
  • assert
  • 97.94 %
  • func
  • 86.29 %
  • block
  • 95.14 %
  • line
  • 96.44 %
  • branch
  • 90.00 %
  • toggle
  • 97.99 %
  • FSM
  • 92.91 %
Validation stages
V1
100.00%
V2
99.48%
V2S
92.63%
V3
10.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 67.773us 1 1 100.00
smoke 50 50 100.00
aes_smoke 3.000s 124.094us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 2.000s 130.578us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 2.000s 122.715us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 5.000s 1226.074us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 3.000s 145.577us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 3.000s 125.177us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 2.000s 122.715us 20 20 100.00
aes_csr_aliasing 3.000s 145.577us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 3.000s 124.094us 50 50 100.00
aes_config_error 4.000s 120.483us 50 50 100.00
aes_stress 4.000s 656.977us 50 50 100.00
key_length 150 150 100.00
aes_smoke 3.000s 124.094us 50 50 100.00
aes_config_error 4.000s 120.483us 50 50 100.00
aes_stress 4.000s 656.977us 50 50 100.00
back2back 100 100 100.00
aes_stress 4.000s 656.977us 50 50 100.00
aes_b2b 8.000s 242.604us 50 50 100.00
backpressure 50 50 100.00
aes_stress 4.000s 656.977us 50 50 100.00
multi_message 198 200 99.00
aes_smoke 3.000s 124.094us 50 50 100.00
aes_config_error 4.000s 120.483us 50 50 100.00
aes_stress 4.000s 656.977us 50 50 100.00
aes_alert_reset 3042.000s 200000.000us 48 50 96.00
failure_test 148 150 98.67
aes_man_cfg_err 3.000s 88.310us 50 50 100.00
aes_config_error 4.000s 120.483us 50 50 100.00
aes_alert_reset 3042.000s 200000.000us 48 50 96.00
trigger_clear_test 50 50 100.00
aes_clear 4.000s 167.505us 50 50 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 307.295us 1 1 100.00
reset_recovery 48 50 96.00
aes_alert_reset 3042.000s 200000.000us 48 50 96.00
stress 50 50 100.00
aes_stress 4.000s 656.977us 50 50 100.00
sideload 100 100 100.00
aes_stress 4.000s 656.977us 50 50 100.00
aes_sideload 4.000s 141.310us 50 50 100.00
deinitialization 50 50 100.00
aes_deinit 3.000s 80.600us 50 50 100.00
stress_all 9 10 90.00
aes_stress_all 33.000s 3004.072us 9 10 90.00
alert_test 50 50 100.00
aes_alert_test 3.000s 74.714us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 3.000s 292.875us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 3.000s 292.875us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 2.000s 130.578us 5 5 100.00
aes_csr_rw 2.000s 122.715us 20 20 100.00
aes_csr_aliasing 3.000s 145.577us 5 5 100.00
aes_same_csr_outstanding 3.000s 205.458us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 2.000s 130.578us 5 5 100.00
aes_csr_rw 2.000s 122.715us 20 20 100.00
aes_csr_aliasing 3.000s 145.577us 5 5 100.00
aes_same_csr_outstanding 3.000s 205.458us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 4.000s 411.146us 50 50 100.00
fault_inject 614 700 87.71
aes_fi 2776.000s 200000.000us 48 50 96.00
aes_control_fi 62.059s 0.000us 266 300 88.67
aes_cipher_fi 61.000s 0.000us 300 350 85.71
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 3.000s 466.054us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 3.000s 466.054us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 3.000s 466.054us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 3.000s 466.054us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 287.593us 20 20 100.00
tl_intg_err 25 25 100.00
aes_sec_cm 7.000s 3866.539us 5 5 100.00
aes_tl_intg_err 3.000s 353.385us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 3.000s 353.385us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 48 50 96.00
aes_alert_reset 3042.000s 200000.000us 48 50 96.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 466.054us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 466.054us 20 20 100.00
sec_cm_main_config_sparse 215 220 97.73
aes_smoke 3.000s 124.094us 50 50 100.00
aes_stress 4.000s 656.977us 50 50 100.00
aes_alert_reset 3042.000s 200000.000us 48 50 96.00
aes_core_fi 14.000s 10032.943us 67 70 95.71
sec_cm_gcm_config_sparse 167 170 98.24
aes_config_error 4.000s 120.483us 50 50 100.00
aes_stress 4.000s 656.977us 50 50 100.00
aes_core_fi 14.000s 10032.943us 67 70 95.71
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 466.054us 20 20 100.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 3.000s 129.083us 50 50 100.00
aes_stress 4.000s 656.977us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 4.000s 656.977us 50 50 100.00
aes_sideload 4.000s 141.310us 50 50 100.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 3.000s 129.083us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 3.000s 129.083us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 3.000s 129.083us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 3.000s 129.083us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 3.000s 129.083us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 4.000s 656.977us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 4.000s 656.977us 50 50 100.00
sec_cm_main_fsm_sparse 48 50 96.00
aes_fi 2776.000s 200000.000us 48 50 96.00
sec_cm_main_fsm_redun 664 750 88.53
aes_fi 2776.000s 200000.000us 48 50 96.00
aes_control_fi 62.059s 0.000us 266 300 88.67
aes_cipher_fi 61.000s 0.000us 300 350 85.71
aes_ctr_fi 3.000s 66.459us 50 50 100.00
sec_cm_cipher_fsm_sparse 48 50 96.00
aes_fi 2776.000s 200000.000us 48 50 96.00
sec_cm_cipher_fsm_redun 614 700 87.71
aes_fi 2776.000s 200000.000us 48 50 96.00
aes_control_fi 62.059s 0.000us 266 300 88.67
aes_cipher_fi 61.000s 0.000us 300 350 85.71
sec_cm_cipher_ctr_redun 300 350 85.71
aes_cipher_fi 61.000s 0.000us 300 350 85.71
sec_cm_ctr_fsm_sparse 48 50 96.00
aes_fi 2776.000s 200000.000us 48 50 96.00
sec_cm_ctr_fsm_redun 364 400 91.00
aes_fi 2776.000s 200000.000us 48 50 96.00
aes_control_fi 62.059s 0.000us 266 300 88.67
aes_ctr_fi 3.000s 66.459us 50 50 100.00
sec_cm_ghash_fsm_sparse 48 50 96.00
aes_fi 2776.000s 200000.000us 48 50 96.00
sec_cm_ctrl_sparse 664 750 88.53
aes_fi 2776.000s 200000.000us 48 50 96.00
aes_control_fi 62.059s 0.000us 266 300 88.67
aes_cipher_fi 61.000s 0.000us 300 350 85.71
aes_ctr_fi 3.000s 66.459us 50 50 100.00
sec_cm_main_fsm_global_esc 48 50 96.00
aes_alert_reset 3042.000s 200000.000us 48 50 96.00
sec_cm_main_fsm_local_esc 664 750 88.53
aes_fi 2776.000s 200000.000us 48 50 96.00
aes_control_fi 62.059s 0.000us 266 300 88.67
aes_cipher_fi 61.000s 0.000us 300 350 85.71
aes_ctr_fi 3.000s 66.459us 50 50 100.00
sec_cm_cipher_fsm_local_esc 664 750 88.53
aes_fi 2776.000s 200000.000us 48 50 96.00
aes_control_fi 62.059s 0.000us 266 300 88.67
aes_cipher_fi 61.000s 0.000us 300 350 85.71
aes_ctr_fi 3.000s 66.459us 50 50 100.00
sec_cm_ctr_fsm_local_esc 364 400 91.00
aes_fi 2776.000s 200000.000us 48 50 96.00
aes_control_fi 62.059s 0.000us 266 300 88.67
aes_ctr_fi 3.000s 66.459us 50 50 100.00
sec_cm_ghash_fsm_local_esc 48 50 96.00
aes_fi 2776.000s 200000.000us 48 50 96.00
sec_cm_data_reg_local_esc 614 700 87.71
aes_fi 2776.000s 200000.000us 48 50 96.00
aes_control_fi 62.059s 0.000us 266 300 88.67
aes_cipher_fi 61.000s 0.000us 300 350 85.71
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 10 10.00
aes_stress_all_with_rand_reset 80.000s 7118.901us 1 10 10.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 31 test runs
aes_cipher_fi 52551116784970682497874119634886887219827677267015359572212324988093146152191 150
UVM_INFO @ 10013595074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 96273503773871986820630378396076154534990966791779815713719370993705103643108 150
UVM_INFO @ 10016239117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 71322545621537771853653778067757523446797998790041741599457533876092520273234 151
UVM_INFO @ 10004646673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 52407507026040037115200770320623811814818478287809596321246625116549533897057 150
UVM_INFO @ 10026850000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 48700025621828391184968140958427475021800752473539319453117478673756206360570 154
UVM_INFO @ 10007694368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 95680683664707631041868073081237295601638678408359193756735063788706774516037 142
UVM_INFO @ 10019030049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 89941793890976523570259970997745907426688246985615807209164793646647095410368 140
UVM_INFO @ 10009625196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 96792585192622854483530516069355537714714234211547081582940112100402642431502 160
UVM_INFO @ 10054337556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 52309316861885244081513507219953547996771444622938445338207194787943305609629 151
UVM_INFO @ 10005265718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 6568384495100831600621718037870187273295933394764222715720582792242605960929 147
UVM_INFO @ 10004563215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 89330470482098645634170984798721858793288526006821802877802891133335499880872 149
UVM_INFO @ 10004286469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 87426591365321237944714282060202528548392760962778577480753431407129647621547 151
UVM_INFO @ 10003104955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 11176864081984678054686094724862907260337819764486667042706336662817306490292 141
UVM_INFO @ 10009690361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 60697023913471029072089844736622634964624870927448734563777948006424875906631 149
UVM_INFO @ 10021944876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 57505465485628980609009820959722379731445754044450452291597176137529196941834 145
UVM_INFO @ 10005826304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 62391756023456683741521841489489121550025201396628198381934663341078501946979 148
UVM_INFO @ 10005882083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 104772565500396771865714184520003551876614251074574733754061544527876429901329 145
UVM_INFO @ 10016786715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 92168780118434242502116803359021217826654188567907567882548031213240629847447 145
UVM_INFO @ 10007991490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 53551129030515105987415657812853610706447073042176343429193591260061595226829 146
UVM_INFO @ 10008712076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 9271392171805252516344378015314067102667401667694338222374298894789456157764 149
UVM_INFO @ 10010755493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 46337932677193274673948477968242693403897737288145565316560165393827395594982 142
UVM_INFO @ 10010824843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 91713224442166083966627879726022016178465026853247016109854249373131716445514 151
UVM_INFO @ 10027644365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 28289526137985221149009013018995892569388545611116830712729143643172384317785 159
UVM_INFO @ 10004666685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 80916872020390828900997474103838470441346522576270991608209410079033013407889 147
UVM_INFO @ 10007704202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 97796671487403585087214209514846768471492581324164671662578424066889176556956 153
UVM_INFO @ 10016231711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 31908668634401959840597400459232382845395207553177954499876394791241215796495 147
UVM_INFO @ 10008241471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 66809818605632338806547297639259504156907897126838990191353087597100139069803 147
UVM_INFO @ 10048801716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 4860110571282255544994077163821602460828665911378834458945134516574753658543 157
UVM_INFO @ 10011651157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 5233845957369380484588361742485211461565742827278464014805622630688857597228 143
UVM_INFO @ 10012347133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 9132126147673200241116820760019914960079937125088660166429729834742522268134 149
UVM_INFO @ 10036934173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 104394800227707002822612502524791547427274643981032911264900421895234952973097 144
UVM_INFO @ 10034217854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 28 test runs
aes_control_fi 53609727069321847684094526686731936536845321677113278036479586005576596781931 None
aes_control_fi 20553220426857964124375056840393777525928386055087301549912285372242738673028 None
aes_control_fi 92271982382505765624081736320561345873904696778007876570469202984356534871571 None
aes_cipher_fi 110598223981718609318872183760445016270226250407739052520736775374739727504884 None
aes_cipher_fi 51550265961647060882338575180098207521911447767255033319018264402426074264823 None
aes_control_fi 111376155085556766820669846394048333287313491202475865791798680113202587365389 None
aes_control_fi 43734515681756004769060759300248286090732887116812238880069833921763008648196 None
aes_cipher_fi 56442505266287543984249590569626409658300140715863318309525106897578518864008 None
aes_control_fi 18933249734832322105297231897223806154533569657760469289798542277714221944413 None
aes_cipher_fi 33305583713130182840374564597768909049130373318392366213162778081219054112545 None
aes_cipher_fi 76355282522232362181289969320524663247261478103068643963635419675911324652637 None
aes_cipher_fi 102905656544705232142564074189867104693787184916611425417980148108569844414877 None
aes_cipher_fi 83015671112145260815395964701031322961693642740642101275911961716678238502136 None
aes_cipher_fi 30009819724721413818988431750504047989569406589291745445076622267903917887970 None
aes_control_fi 75606181667653174265002752650631696104314507077947818671238778409327118458306 None
aes_cipher_fi 20510197428958915551311141390684918991307232780676730473655790760048146970057 None
aes_cipher_fi 26582896027144375000879336892221279265462136201603215028105292072599777722981 None
aes_cipher_fi 102949383994545032023663830935676901026798710382970141338197267263843015173657 None
aes_cipher_fi 46519990140739465007670628099783948425522115574878537423003516349512926624226 None
aes_cipher_fi 59792838431721377859416321889566460764887920347055059318317968988105165537077 None
aes_cipher_fi 57346592363856910641357536035476565716400364532646254492919224750195427754175 None
aes_cipher_fi 26064285935317626944518831974342676374780530447643885167523792533494377567940 None
aes_control_fi 114143394549612397617912474110365801597174514645806566150032475374204989824867 None
aes_control_fi 40266886124194498696011654217324188992932904943271259847545449451694283647947 None
aes_control_fi 107185928003110113957581979412354418878379685355092100227491531125164674137799 None
aes_cipher_fi 36515263019293377484940384809507177555607707859833898357032993447989581030253 None
aes_cipher_fi 38964346556902117691581308833823877001888394776708907837509799726447333224462 None
aes_cipher_fi 15809476573973954761091320775086610481973569166501811909746909902429813112212 None
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 24 test runs
aes_control_fi 74138729423141783624822262941265833382513481251109276263256008986810326013720 142
UVM_INFO @ 10011528923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 26826855887638190009366573994596727450465733712937131546177950009846397665699 152
UVM_INFO @ 10016964396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 90362954091015138175779518261084976909776788331711927243706638039873124952264 148
UVM_INFO @ 10009380345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 29025693383506949887161723573563366932224986171787815699186686685172144189308 155
UVM_INFO @ 10007223714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 102853768476049718899655551856408974977045762392713222259042010935438808319489 154
UVM_INFO @ 10014760447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 92879655308725412435933469432380908257596456220187552333576781088460147370455 143
UVM_INFO @ 10014804816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 115470199201799648173519979976942335126280509113452703320555006665366043216137 146
UVM_INFO @ 10003940111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 102588721371426605992050399321911206695118197222341205741958926869041508049218 155
UVM_INFO @ 10008884209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 67569186748448544635777278420264833267958513585795293782077476904927552729992 145
UVM_INFO @ 10015555719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 60308457875344335855140243907351700893897535026388663446667303279115240794489 152
UVM_INFO @ 10011653086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 113314691319606894797824545351243720620035415003866571400767918213263811432828 147
UVM_INFO @ 10013471346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 104888975655792538580291094864142908018271964980933175793683473702844707690658 153
UVM_INFO @ 10013686560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 9336016558201666887503973163683132280503638975494661413242360726656288431467 147
UVM_INFO @ 10018998460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 43156864361954146851523304301289193591097890733920655137199615080668294101624 145
UVM_INFO @ 10004988222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 29475820117732183306640375728018997608700343772187427494166910938397265248809 149
UVM_INFO @ 10022095027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 18054873645739421297069453860431606711957323500434756795957976562921204108181 157
UVM_INFO @ 10014722637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 81041743150963075142111690025662869037206520067904310141147798559360818887659 155
UVM_INFO @ 10006160076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 63365254799680284862962928564730700525287592311492327670366218907744523813955 155
UVM_INFO @ 10022259376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 12889166738167222956958901519110964822463231830593759969883670484440548997539 150
UVM_INFO @ 10002441184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 15451914658961212950404111457807423537671069450002125013938019289738334844031 147
UVM_INFO @ 10006446804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 79131256820694675678840282060329559644113802471625183195924468660403278541916 152
UVM_INFO @ 10016951946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 45734094830798309818165410015179135332997575433696867418591931997492056695185 146
UVM_INFO @ 10043839434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 47764006957999277767251229541448283796343361080957530830051756992033306257436 143
UVM_INFO @ 10020156312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 5139096797171865184422790441235406740841486689356761827813853379469698122914 143
UVM_INFO @ 10052126213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 3 test runs
aes_stress_all_with_rand_reset 94719623375918714150622986015016939244011069443614358744551781654182156228855 885
UVM_INFO @ 973918833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 33756967488287221985755932046406131728864266135857577873127323698743421466515 323
UVM_INFO @ 1190022828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 2039992410424247561205980021016433289041142849840104504120226000536937027853 440
UVM_INFO @ 258677115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 3 test runs
aes_core_fi 115626514271266588050527991490646397733492550081463297146789284452768470073673 143
UVM_INFO @ 10032943065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 20323934888354942231153332741517553041614476062787011447173396817028769762722 146
UVM_INFO @ 10012646286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 93223711821128327270518854078726330880465799352746017561646297207214766765996 147
UVM_INFO @ 10008982517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:307) virtual_sequencer [aes_alert_reset_vseq] Expected GCM phase GCM_AAD, got GCM_TEXT 2 test runs
aes_stress_all_with_rand_reset 85540659641442633905677502951465012103202425935131717621531675541434222327126 255
UVM_INFO @ 467496039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 41756980766500746219244971407618230849568031379008110677759404419305890827361 306
UVM_INFO @ 335807308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 2 test runs
aes_stress_all_with_rand_reset 72567074372055415697316938253922493668398748401508080430754279664458517987272 171
UVM_INFO @ 44870954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 2616408300925597065380104484913571293993589028240713249412883644445683952784 901
UVM_INFO @ 283371948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
aes_alert_reset 77146966079846792855937411387168433585575883908688533037849577912626462609423 21986388
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_fi 12761090423728461063051594257054191567017714570798625216065003129252030918209 18510329
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) 1 test run
aes_cipher_fi 78248984118852201336550035205470123006621135965938558229725884175327413674027 144
UVM_INFO @ 10035312900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:307) virtual_sequencer [aes_alert_reset_vseq] Expected GCM phase GCM_AAD, got GCM_INIT 1 test run
aes_stress_all_with_rand_reset 15659883666843366306733942528137274328493263303698536002722849480396772936018 2292
UVM_INFO @ 1236997975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:616) scoreboard [scoreboard] 1 test run
aes_stress_all 2370345988410211337776866997997662803625097777506791266917727494401620157606 50956
----| FIRST ITEM DID NOT HAVE MESSAGE START/CONFIG SETTINGS
UVM_INFO @ 1151474219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1142): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) 1 test run
aes_stress_all_with_rand_reset 110504453903468909865679553499682668940977205255910939705411900283257525008438 4747
UVM_ERROR @ 7118900949 ps: (aes_core.sv:1142) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
UVM_INFO @ 7118900949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 1 test run
aes_fi 57050853033218159874646195346542333040555845939431547482588849028820652616758 298
UVM_INFO @ 31358076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1112): Assertion AesModeValid has failed 1 test run
aes_alert_reset 100359868144996925992503227418676841323463793501614890482361788360003145399773 2833
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 36758728 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 36758728 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 36758728 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
UVM_ERROR @ 36758728 ps: (aes_core.sv:1112) [ASSERT FAILED] AesModeValid