| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 5 | 5 | 100.00 | |||
| aon_timer_smoke | 3.000s | 556.099us | 5 | 5 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| aon_timer_csr_hw_reset | 25.000s | 1304.058us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| aon_timer_csr_rw | 3.000s | 355.038us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| aon_timer_csr_bit_bash | 35.000s | 7311.236us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| aon_timer_csr_aliasing | 29.000s | 601.004us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| aon_timer_csr_mem_rw_with_rand_reset | 3.000s | 449.823us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| aon_timer_csr_rw | 3.000s | 355.038us | 20 | 20 | 100.00 | |
| aon_timer_csr_aliasing | 29.000s | 601.004us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| aon_timer_mem_walk | 2.000s | 558.326us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| aon_timer_mem_partial_access | 2.000s | 304.366us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prescaler | 15 | 15 | 100.00 | |||
| aon_timer_prescaler | 118.000s | 58122.501us | 15 | 15 | 100.00 | |
| jump | 5 | 5 | 100.00 | |||
| aon_timer_jump | 3.000s | 722.567us | 5 | 5 | 100.00 | |
| stress_all | 15 | 15 | 100.00 | |||
| aon_timer_stress_all | 200.000s | 126398.348us | 15 | 15 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| aon_timer_alert_test | 28.000s | 455.924us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| aon_timer_intr_test | 3.000s | 494.057us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| aon_timer_tl_errors | 9.000s | 552.140us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| aon_timer_tl_errors | 9.000s | 552.140us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| aon_timer_csr_hw_reset | 25.000s | 1304.058us | 5 | 5 | 100.00 | |
| aon_timer_csr_rw | 3.000s | 355.038us | 20 | 20 | 100.00 | |
| aon_timer_csr_aliasing | 29.000s | 601.004us | 5 | 5 | 100.00 | |
| aon_timer_same_csr_outstanding | 9.000s | 2685.614us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| aon_timer_csr_hw_reset | 25.000s | 1304.058us | 5 | 5 | 100.00 | |
| aon_timer_csr_rw | 3.000s | 355.038us | 20 | 20 | 100.00 | |
| aon_timer_csr_aliasing | 29.000s | 601.004us | 5 | 5 | 100.00 | |
| aon_timer_same_csr_outstanding | 9.000s | 2685.614us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| aon_timer_sec_cm | 12.000s | 4711.047us | 5 | 5 | 100.00 | |
| aon_timer_tl_intg_err | 24.000s | 8602.506us | 20 | 20 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| aon_timer_tl_intg_err | 24.000s | 8602.506us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_max_thold | 3.000s | 708.995us | 5 | 5 | 100.00 | |
| min_threshold | 5 | 5 | 100.00 | |||
| aon_timer_smoke_min_thold | 3.000s | 633.592us | 5 | 5 | 100.00 | |
| wkup_count_hi_cdc | 5 | 5 | 100.00 | |||
| aon_timer_wkup_count_cdc_hi | 8.000s | 2955.963us | 5 | 5 | 100.00 | |
| custom_intr | 10 | 10 | 100.00 | |||
| aon_timer_custom_intr | 4.000s | 703.890us | 10 | 10 | 100.00 | |
| alternating_on_off | 5 | 5 | 100.00 | |||
| aon_timer_alternating_enable_on_off | 33.000s | 4266.183us | 5 | 5 | 100.00 | |
| stress_all_with_rand_reset | 15 | 15 | 100.00 | |||
| aon_timer_stress_all_with_rand_reset | 45.000s | 65458.899us | 15 | 15 | 100.00 | |