Simulation Results: clkmgr

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.63 %
  • code
  • 80.12 %
  • assert
  • 93.80 %
  • func
  • 76.96 %
  • line
  • 91.70 %
  • branch
  • 94.65 %
  • cond
  • 89.25 %
  • toggle
  • 100.00 %
  • FSM
  • 25.00 %
Validation stages
V1
71.43%
V2
61.91%
V2S
31.06%
V3
2.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
clkmgr_smoke 3.740s 193.447us 50 50 100.00
csr_hw_reset 5 5 100.00
clkmgr_csr_hw_reset 1.830s 140.876us 5 5 100.00
csr_rw 7 20 35.00
clkmgr_csr_rw 1.690s 55.190us 7 20 35.00
csr_bit_bash 0 5 0.00
clkmgr_csr_bit_bash 6.130s 326.339us 0 5 0.00
csr_aliasing 4 5 80.00
clkmgr_csr_aliasing 1.920s 54.680us 4 5 80.00
csr_mem_rw_with_rand_reset 9 20 45.00
clkmgr_csr_mem_rw_with_rand_reset 2.620s 113.801us 9 20 45.00
regwen_csr_and_corresponding_lockable_csr 11 25 44.00
clkmgr_csr_rw 1.690s 55.190us 7 20 35.00
clkmgr_csr_aliasing 1.920s 54.680us 4 5 80.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 50 50 100.00
clkmgr_peri 1.870s 62.760us 50 50 100.00
trans_enables 50 50 100.00
clkmgr_trans 6.790s 410.411us 50 50 100.00
clk_status 50 50 100.00
clkmgr_clk_status 2.870s 146.437us 50 50 100.00
jitter 50 50 100.00
clkmgr_smoke 3.740s 193.447us 50 50 100.00
frequency 0 50 0.00
clkmgr_frequency 1.490s 43.499us 0 50 0.00
frequency_timeout 0 50 0.00
clkmgr_frequency_timeout 1.240s 22.804us 0 50 0.00
frequency_overflow 0 50 0.00
clkmgr_frequency 1.490s 43.499us 0 50 0.00
stress_all 3 50 6.00
clkmgr_stress_all 7.460s 426.761us 3 50 6.00
alert_test 50 50 100.00
clkmgr_alert_test 2.860s 133.549us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
clkmgr_tl_errors 10.680s 896.713us 20 20 100.00
tl_d_illegal_access 20 20 100.00
clkmgr_tl_errors 10.680s 896.713us 20 20 100.00
tl_d_outstanding_access 18 50 36.00
clkmgr_csr_hw_reset 1.830s 140.876us 5 5 100.00
clkmgr_csr_rw 1.690s 55.190us 7 20 35.00
clkmgr_csr_aliasing 1.920s 54.680us 4 5 80.00
clkmgr_same_csr_outstanding 2.360s 87.666us 2 20 10.00
tl_d_partial_access 18 50 36.00
clkmgr_csr_hw_reset 1.830s 140.876us 5 5 100.00
clkmgr_csr_rw 1.690s 55.190us 7 20 35.00
clkmgr_csr_aliasing 1.920s 54.680us 4 5 80.00
clkmgr_same_csr_outstanding 2.360s 87.666us 2 20 10.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 25 4.00
clkmgr_sec_cm 120.780s 10142.589us 1 5 20.00
clkmgr_tl_intg_err 92.060s 10035.924us 0 20 0.00
shadow_reg_update_error 15 20 75.00
clkmgr_shadow_reg_errors 2288.660s 200000.000us 15 20 75.00
shadow_reg_read_clear_staged_value 15 20 75.00
clkmgr_shadow_reg_errors 2288.660s 200000.000us 15 20 75.00
shadow_reg_storage_error 15 20 75.00
clkmgr_shadow_reg_errors 2288.660s 200000.000us 15 20 75.00
shadowed_reset_glitch 15 20 75.00
clkmgr_shadow_reg_errors 2288.660s 200000.000us 15 20 75.00
shadow_reg_update_error_with_csr_rw 0 20 0.00
clkmgr_shadow_reg_errors_with_csr_rw 2.140s 78.379us 0 20 0.00
sec_cm_bus_integrity 0 20 0.00
clkmgr_tl_intg_err 92.060s 10035.924us 0 20 0.00
sec_cm_meas_clk_bkgn_chk 0 50 0.00
clkmgr_frequency 1.490s 43.499us 0 50 0.00
sec_cm_timeout_clk_bkgn_chk 0 50 0.00
clkmgr_frequency_timeout 1.240s 22.804us 0 50 0.00
sec_cm_meas_config_shadow 15 20 75.00
clkmgr_shadow_reg_errors 2288.660s 200000.000us 15 20 75.00
sec_cm_idle_intersig_mubi 50 50 100.00
clkmgr_idle_intersig_mubi 4.980s 298.200us 50 50 100.00
sec_cm_jitter_config_mubi 7 20 35.00
clkmgr_csr_rw 1.690s 55.190us 7 20 35.00
sec_cm_idle_ctr_redun 1 5 20.00
clkmgr_sec_cm 120.780s 10142.589us 1 5 20.00
sec_cm_meas_config_regwen 7 20 35.00
clkmgr_csr_rw 1.690s 55.190us 7 20 35.00
sec_cm_clk_ctrl_config_regwen 7 20 35.00
clkmgr_csr_rw 1.690s 55.190us 7 20 35.00
prim_count_check 1 5 20.00
clkmgr_sec_cm 120.780s 10142.589us 1 5 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 2 50 4.00
clkmgr_regwen 1.450s 20.863us 2 50 4.00
stress_all_with_rand_reset 0 50 0.00
clkmgr_stress_all_with_rand_reset 29.970s 2653.194us 0 50 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 102 test runs
clkmgr_frequency_timeout 17542405580192529870927916964794406615532526607697886649829192676745744185909 78
UVM_INFO @ 3930801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 44958849109880152103353704755767176181520157709647732145962218635894239379152 87
UVM_INFO @ 12301990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 81522640394867664427011383932923878084564044741658558469242903583164693078036 77
UVM_INFO @ 2781398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 26536314780549800135948319858121413256235123794192579282862820877408360134188 78
UVM_INFO @ 4156071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 44489787749814675398802064607736582718004379606664175496211666764465446459972 77
UVM_INFO @ 17240542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 62346265610203037005846683289959226734088763070216319957832702717286777727479 78
UVM_INFO @ 6141107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 101255963043653548386882055835461305532511483067774328607668760438536771524381 79
UVM_INFO @ 9815842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 9668835973322553396893451390460113491088866405636134500218206675929500672890 78
UVM_INFO @ 4503189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 24612349988791359722141916715090655195485230696577957468392396695561602134376 78
UVM_INFO @ 3623183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 17776087263468773981313413850665445040092524845349728216808113065017458336167 78
UVM_INFO @ 3354906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 109953818088438328905793230516354549215161373658191310225957916555202979044651 77
UVM_INFO @ 4626181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 52231970377485347610879229218507812120918643487613704686345420249400258915001 78
UVM_INFO @ 3143670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 19699903910536667884454888566802883559827785163034628294989242474968593100265 79
UVM_INFO @ 16649958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 48250598418239815832072867908587688972996121443321789467570659468757713564848 78
UVM_INFO @ 22803913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 74700270859352196371787783199917058969158024319540638388581715143590815287766 131
UVM_INFO @ 84031551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 105946777890052671609971087045921114420266918635017413986618285020126588445041 78
UVM_INFO @ 3725955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 31855631301906348850418059272823209110085097471904205719021514048599396335898 77
UVM_INFO @ 3184822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 33659460195974873348747157678434274103172258129684399183139763482818700377625 78
UVM_INFO @ 8136659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 15134856331136945843916743883163649898968456031307254152345754203495494341635 78
UVM_INFO @ 16475539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 106257179457950832589114912463648306771670516698713869298451155992822339365977 91
UVM_INFO @ 37115921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 87774453424619405022115882384681980763832528271181993383764910664786159252152 77
UVM_INFO @ 396849283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 14383767393649545781864967169195534151332020322244690292581111626056473469038 78
UVM_INFO @ 2303303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 5621364371813404392673156057582844306931686326096429013579246469493697515451 77
UVM_INFO @ 5393124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 10974807424328204214743388008871831707171327616217492063132286646468695711444 79
UVM_INFO @ 13444046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 3205875716009031115198935541437333114947648792410227485783933042111057935275 77
UVM_INFO @ 2994816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 5663914484244252898966567899301132499212677917801209658798858581618711543900 77
UVM_INFO @ 4758243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 41621168555305793951262692328046321627101415856379722326362895178749931556146 77
UVM_INFO @ 4263540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 65034935864908273260898314662962584218400416495738123873125806171423523764547 77
UVM_INFO @ 37509407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 38936318099384792349624211931232203668929878997771053395102181448703443994151 78
UVM_INFO @ 3445119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 52530752938732780576922078289126989527143998314950744325757225646816124967434 77
UVM_INFO @ 74532179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 83539158474547671559323932433402458835056944399918815622439087683873590519832 78
UVM_INFO @ 5712500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 69955368685457211312740524448943492805939924287725343829965871810046306737187 79
UVM_INFO @ 6277587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 56926661304624852337485935184434800166660894543240023695940004065364463981281 78
UVM_INFO @ 6625421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 12896553980551467481470004003950566370669580553356903204729656986251812409696 78
UVM_INFO @ 4648782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 98642225815623153579385151315832762661544530691870153400255524768205458362511 77
UVM_INFO @ 49442257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 12094049965879978401105800491344723982057794903178985065727352485062875415585 78
UVM_INFO @ 4256954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 106628078082622640696550966631609154563197561921183192526341956913899908631236 79
UVM_INFO @ 5244049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 86688584490616562229747158640556612957756787235216422952617368608286797062971 77
UVM_INFO @ 3357875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 48630659304580816317792244846948084189204735110154761661627729954984604759880 78
UVM_INFO @ 5898259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 77270014072257359071994616911883386283634043378038631308773862110585906880952 137
UVM_INFO @ 143172647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 91167617777537097755901438353890563241827135883380461379686227417453034360281 89
UVM_INFO @ 66684499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 6881403928473012921659854583039203146010465863421306158080547724943772807113 78
UVM_INFO @ 9956144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 98148023195505580422034074222681913574621658210414093111364918260977386511367 144
UVM_INFO @ 892613789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 108351813530826932216486491756649027464790627507133078359167772735990487676359 78
UVM_INFO @ 3031383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 33442913177885830187411508913024499644769780248747048435103810977105860547045 180
UVM_INFO @ 192120728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 30129247289223532614759992209526561068253202135067000179945303123128267134208 77
UVM_INFO @ 4186159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 64381128689368474941232318646413719018715807205005039385809077411040461285808 91
UVM_INFO @ 897071503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 1814493116832552877965884898766404114190930421587813008449234043303556127042 77
UVM_INFO @ 39013600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 72668810037296461008568508154788547319123768270700696696974034240484671780779 78
UVM_INFO @ 4170297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 95925970104269894992631931010056815571004930027474828271394739370471114925456 214
UVM_INFO @ 104236984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 9389760869567100736832411026671279342958306525134907997840679682835935551068 78
UVM_INFO @ 7275484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 80376683315773176807316851578974129877885545412299009083629294885464354171489 77
UVM_INFO @ 5546042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 104130340667932767234388260974302702697809564773070866321642461870409296643729 79
UVM_INFO @ 2673836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 47604577868515788140601224992625427262686555566576193127463819705029907195838 221
UVM_INFO @ 224140674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 6124242686040241716018812235089582452635353361721197850180074698398067307245 78
UVM_INFO @ 15858278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 60687575999980312634447885282006097536827765460707282237590367032515377229469 103
UVM_INFO @ 19275523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 82975033457182276877638881188071147766321817652935844631097142089315670713364 78
UVM_INFO @ 32664058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 80394694258851598586006987488905264087222786841150692404504927985492475194234 78
UVM_INFO @ 3342671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 63135785399779365424697937971648987849275804730356666336848477217264288070021 86
UVM_INFO @ 1127083257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 10289109730826609247471647410612015641135095910224820124348705548200490464876 134
UVM_INFO @ 217981876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 24643525106013992970004328398262999322065154929981724909812949738900309240433 77
UVM_INFO @ 2357645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 574242566027950643265715801172797199950656284360849279113340951879050680262 119
UVM_INFO @ 287268721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 80320631887095403055938011196514768044738693154233131583112569522172304866293 78
UVM_INFO @ 13954781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 108662227492459489550163567027664331188854249607740898140223608648565827366290 78
UVM_INFO @ 3167698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 22323596880880108434774095467585281193363905362549347878351355938038648139356 131
UVM_INFO @ 79264165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 10631369821169698514070567679315897484352887367177457228292192783664447932924 77
UVM_INFO @ 6775687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 58964538543100821162214463588605388626541058113410150682350183064897742675302 78
UVM_INFO @ 7356065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 2278528561318465488362930250757325355735528505725420694691958786976928351648 166
UVM_INFO @ 137774441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 69025286638895635641627492615796628783112117903103082898882700913331510959187 102
UVM_INFO @ 33976508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 59900759380512722474220062333531180093008547294445233416450724815507439981303 78
UVM_INFO @ 3286127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 43901930867789733082824886814680931805750097276706234604396926898027510976404 78
UVM_INFO @ 6424670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 39007352274688358969225191170662017305846547454771859507591903118176132513944 205
UVM_INFO @ 116483194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 103750878520938585987961480123875467462997441535600543971263527134745449901144 78
UVM_INFO @ 2428911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 87805701714733513581855386082047247892805627405502578219911064977596469583339 160
UVM_INFO @ 495256861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 75854659844059223143202290405952984745544311274471164296280143632381855890784 77
UVM_INFO @ 123691655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 71768734072019569320050509270661727830458101565163354498014583995259205791638 77
UVM_INFO @ 5461915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 19363056970738723861159404610349085073969484627338532419951041656850131738098 78
UVM_INFO @ 3446874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 8102284724736018114330940454296619708432780907191169982600749311858177768848 133
UVM_INFO @ 61124951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 62793314886642566192143611259834739909900558713181616803450093974716703406871 78
UVM_INFO @ 17097732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 82965050236623625002392292203578662442950878450717507472082394982090842061369 78
UVM_INFO @ 2252967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 73522858475896390162138524366416065529003128745311626559674520231060262557541 206
UVM_INFO @ 312531187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 101360616616374967851200114431626242675868661419114407699791905921907099013026 77
UVM_INFO @ 3482944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 29283440766889559927884639829309535966531636027961514236544102845415134938360 78
UVM_INFO @ 4222679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 12686566423445408890935235188605221051270567532067672584424711376573950285182 78
UVM_INFO @ 4392267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 24241618558978791163029872509750101946488042790211376158373814717068139190422 79
UVM_INFO @ 24464372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 79227889391701545320960250577420377836544194725168392562724657972145374418376 77
UVM_INFO @ 4676728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 87720912738389646373997094600081798506417043474711032725906965494284633393055 79
UVM_INFO @ 9544813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 115208539323515564974859882743702468310014028890587601809072479302397587061993 77
UVM_INFO @ 15149000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 584139590812945692443486477716353261616186991047890361929922488741544655773 78
UVM_INFO @ 4065052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 113370355647843599401875769208616922399635850380628313344207620849936521655034 77
UVM_INFO @ 45393770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 71056506866591425812538246881593913285662118007257305900543677419422717526045 78
UVM_INFO @ 3092577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 10926479225397165705318631972610029743865313243376691367805260552686547191222 93
UVM_INFO @ 145188912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 81564946233249112135291130124597330900521807358669850889237501328357743108930 78
UVM_INFO @ 3684408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 108236730201336795876081049473356453609207279660180755855649227181227773986402 78
UVM_INFO @ 3349813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 108005652485097309919918418409665006542141826689224003719376184953416135634119 144
UVM_INFO @ 74238478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 40155513302770662026553503277319308036486390693035068722431980220140626978614 113
UVM_INFO @ 23151144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 40290869014281343104813108099748524156180828773724600986056285923263925836303 78
UVM_INFO @ 10775233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 96797557863496714807604770582660864350947528063882473799341120769218044148543 79
UVM_INFO @ 4322738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 77374424657293668135431805067266498683938883733193770604417916227258582547141 78
UVM_INFO @ 7697771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 99084528874407832614177151303489885507577765095378127453179831806982295325140 79
UVM_INFO @ 7959762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 48705817056009499540872123723384246774320842193784563490773755408932645226893 78
UVM_INFO @ 41420563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency_timeout 52644898742668745888802067904981673463644413365321414664721410392693755077081 78
UVM_INFO @ 4593025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 95 test runs
clkmgr_frequency 97616991088067885808034006003179785562059796799554155953191134463954036792854 75
UVM_INFO @ 13858467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 2966250797720644308006062242855003609386278016848164588098972866476689922397 84
UVM_INFO @ 426760876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 13727430383542078354939740372114087422689561976232736888902468866007353934031 76
UVM_INFO @ 7832111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 80670794808821509804262869685026802168299640937499686151618241362869956175351 89
UVM_INFO @ 59370280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 68679899765948585508997588541197170293688909547316175867721254808912709002053 75
UVM_INFO @ 5200243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 26656627497882255320710116185581485999960566346753520523986316351418937581646 75
UVM_INFO @ 5181494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 57850652217797667222445968602857541438730865835013650060935044427069064544100 123
UVM_INFO @ 151682288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 58358321534080567900500629144527103748400651688290193895980635816160983988151 76
UVM_INFO @ 3788048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 94566687912321920033249259215815092563498592854934230510072825597870028213128 76
UVM_INFO @ 9681490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 101362520957666612630831452933517515873864914619020139998906192946854846572650 76
UVM_INFO @ 8575307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 10037239117949906003791381701977450136427712073918261625251643484134669090518 78
UVM_INFO @ 8350664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 46469522655072366263564570701869456981630442622481360700808154155691899776603 244
UVM_INFO @ 328672330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 106642664458904563865236409015732034506476666345641889948934549797266425134056 75
UVM_INFO @ 9209514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 27951177374429500637828018093268342612699553885864746080975083889688074017875 298
UVM_INFO @ 215409271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 39655931377069945944465935879756759447109642861729448451338439029775975703442 77
UVM_INFO @ 24003194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 62388969505025346850279219254964661122459057757094418073679887310106072566033 76
UVM_INFO @ 14439919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 94537999114647975198511769173515102713340321199196095922957688460215277238143 169
UVM_INFO @ 508165891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 96571367551659876012154653440050606986893991565121506291013111655757744137336 76
UVM_INFO @ 43498716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 73610308814668822225881144276191380679562548868713773452754455080128711184287 76
UVM_INFO @ 22696781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 107030314081828167963874685796660838668414731585259571172243349978969104044776 75
UVM_INFO @ 12206118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 63024299683341824298497179733350566064635635864460118830452025506924116394234 76
UVM_INFO @ 17681928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 80615088940850001960561324480460224885806829577525189895027023770241625435157 78
UVM_INFO @ 27204821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 51536537710614574234712835941577223895472613908910882564565321419917577578058 76
UVM_INFO @ 7548282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 16752798019587203072839034675977390557936392194071754624978919260104293576601 76
UVM_INFO @ 6941272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 18993532157402081033002637734700989884823318953896125186878071048885619297424 78
UVM_INFO @ 22515849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 111152243128210011231839262471005621430316091351029710065912712033027633859703 77
UVM_INFO @ 14985102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 1225141131188208154410246390715962873684535870703476248505781203547064816761 75
UVM_INFO @ 13337473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 64410090414606769158114365051320707725342089669185326204647500037905230015173 77
UVM_INFO @ 59847333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 103958432167307764173467583200698704339531703599717513119750260586787882089426 127
UVM_INFO @ 185009753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 90281606702754689849334521973734413423711190310144318997538663176488155884106 75
UVM_INFO @ 5890995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 20394337244541567519790276260890641687779265593361884414725963417684204790004 75
UVM_INFO @ 7587088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 36614643971714104988422705665962718428798701711505728691863378266174044536544 75
UVM_INFO @ 15231641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 14274126114545812386531937495086485249580430353723498565611822996404654791259 201
UVM_INFO @ 1429489979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 53733399923523949098897323684217826943879561399977941146638423638400452496098 76
UVM_INFO @ 13315352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 47313685245495641062491584508544779256241111399214982327618393623603271465989 139
UVM_INFO @ 372195166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 86709296970607622865395490170435998746091046749559710085099517141006359320507 76
UVM_INFO @ 11313967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 65637224240421931745499866873077724753051831096876351533186171862284640812576 139
UVM_INFO @ 2653194074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 67063642090725357925204313296950876471707135481182791942709909955420434683787 78
UVM_INFO @ 11121507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 19941202458938644537388701241100468061446938409830122288108502430114097373647 75
UVM_INFO @ 4771295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 43502389472207439241646176098536694441327622491086181215614830401071244950972 80
UVM_INFO @ 62587193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 69017717481039243757627476492978526560658220320371725898983200379383724495078 148
UVM_INFO @ 45415301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 95541138912795494220736435237848505091069213496221756398111318704172036469361 76
UVM_INFO @ 5154033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 63255644866086941673215252647055471317692155359759412957675417653233140342876 100
UVM_INFO @ 155787373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 81555636949417403206037052600187268794907982156631461918141217177978844911718 76
UVM_INFO @ 3780859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 100075527762924798294940796846566976548634152176816645337077685182041309977848 78
UVM_INFO @ 27922408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 76380340837462379241332443730180317401540263139192649591640835207453340957940 76
UVM_INFO @ 4215477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 86316494122015003013472162977878540549412548968482815706375743627180196960839 76
UVM_INFO @ 147154076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 4604014500024953605432088257579884855082309557009999449707843135209722035769 76
UVM_INFO @ 36516581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 75635805677498625719758651970366008259764806631565932809861596223413300897905 76
UVM_INFO @ 8285798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 34809648502748313585463817226547336742976247461547997300571452332460583054267 76
UVM_INFO @ 6410341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 94746481848735084315002815841352534602399966199290147176219425962229754264211 75
UVM_INFO @ 12370023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 50856412174060492221266606773729308911693079007051056080886892370921295130667 78
UVM_INFO @ 10047926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 101468770605698799634748196202342742204328503315080309601255907412248282480380 76
UVM_INFO @ 7106528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 73764337581920279051419600256353239928079098457306763939550338299355913174527 184
UVM_INFO @ 135536375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 72103870804395254196175618982852981456935902542669499039785566635328760351017 76
UVM_INFO @ 7679770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 47865735414939928460309312752546986576235338422813407572301868164800047603647 76
UVM_INFO @ 15426530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 23940627126225536050689329996790981640757527983756521679308956941374822309578 78
UVM_INFO @ 14295298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 37027124608472698509068945889455309133063347347057089646886474617423327124368 76
UVM_INFO @ 5844011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 55709835343953099405962921956296272211534307362186627500988531218665546721848 76
UVM_INFO @ 23790541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 61457955157569507546221718358220130585950637295496781783306217401107656619767 75
UVM_INFO @ 7994245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 75962741486953871988974522559333676830781541062704016411567812822648878062608 77
UVM_INFO @ 220590473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 109617612136050803221796560899408234941201750318134121465896366123406415043847 75
UVM_INFO @ 7291733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 95302152386997256841190485873523389600590331857791523914891940756184012691671 90
UVM_INFO @ 96867005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 107699735408796764069935025760488852772277139523178067042162460858745060631579 75
UVM_INFO @ 8444192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 4963832562400352576577469698610801049132595546256029647974165268767473148397 76
UVM_INFO @ 4748459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 44103846853237481039584610763545424888909751291495139360957964693436972210512 78
UVM_INFO @ 51204370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 38856618309824422467093768157217267917745055458005171329321734764574761326997 76
UVM_INFO @ 28094065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 83318380286892576002593982891198260810898821698844331813674699591284222011437 75
UVM_INFO @ 13747027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 42543802099736428276837609742780308568601050215592440392526123908108164930537 78
UVM_INFO @ 16287718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 31047721304120111790810505174786789101447537247145803303949457055553529647535 77
UVM_INFO @ 28490801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 38941386538110456698726516571669526361809363969167117925404716169097506267550 78
UVM_INFO @ 9629223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 26253175035284184133586129357623068562379829588068352181896434880443200992912 87
UVM_INFO @ 94342146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 15827988641728657940521271213295455369739845345907211693065358354544230586632 75
UVM_INFO @ 49469942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 88190193332178813580577589200601150088619253392256660566206395640243176793430 76
UVM_INFO @ 6117651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 89720878609673719851966691800122134318358665074663116495628105880350124431672 76
UVM_INFO @ 6434262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 75345477260921038099597385216745469679545996464891462082073310130770395342982 92
UVM_INFO @ 18035357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 74376257834515556317948640588363797069682715618841622514016734053213542119132 76
UVM_INFO @ 9270118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 102120245339890491170909178196059703783182252545241808192416351674630452917989 145
UVM_INFO @ 189807254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 26925302740707831540664598364106304507621538119966366803198477064329482700091 76
UVM_INFO @ 89998574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 101912134125936659707627471559458788239800528565114015764954334220053398380906 75
UVM_INFO @ 8169144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 33163944349354513444388444000972434647854385860250677751590106394868280756078 78
UVM_INFO @ 6169879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 69818078324579201963975448967726834672728802662368659337585649966164519183777 75
UVM_INFO @ 112683013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 7604252768231960135084701987148905265700103387474470082091018574447227705972 76
UVM_INFO @ 9121225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 69914001267847840179497926328950009412323837887665463452451737268367263436967 75
UVM_INFO @ 44604478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 90157773823357086856449982300154456517369590848888891736696432261756802102881 76
UVM_INFO @ 6462744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 22995978934221310403585845290688136492674359960844019956481138098384411973985 76
UVM_INFO @ 9713432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 108701451046909037349664124955004969502310131252386944623175385422742826964472 78
UVM_INFO @ 16670120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 49340626171116670977305425970949702131578894816962071007026294589828814246638 80
UVM_INFO @ 14320917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 18578792365930118781084507651676152034449266575010302342003932398387271399451 76
UVM_INFO @ 21993007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 9650073852301211428160914174158434444892744693492083587695569147723931657793 76
UVM_INFO @ 7121569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 53194343340143653367733445516374257136455131118335766719554059128574704203966 75
UVM_INFO @ 13637839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 35832870170056647544851016947004361394737291201077164793139316950276089473704 76
UVM_INFO @ 6817713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_frequency 43450726595468538962282048376494004791363074868823934833693821906398549928963 76
UVM_INFO @ 15718872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 111970651083143788311553843179675098426734538477713645716693479249642384170503 78
UVM_INFO @ 15844025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 62428061397773094691354284744823217432216110122797663423666827242784024162595 75
UVM_INFO @ 6153266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 34 test runs
clkmgr_tl_intg_err 41850879880623650452805147336365193365509747241755749518936804971008726829380 86
UVM_INFO @ 9849658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 67561111659013163939103152940947818895096551918424256208849443966061240128389 76
UVM_INFO @ 5703268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 87470555306628763828453195827508474297966530403088842448039512824420460913648 75
UVM_INFO @ 2268868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 26331665564362712002491625736688043884262310282021952377330419736839059493697 75
UVM_INFO @ 9903011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 36589557587535481218542081960900787773807496665337229311068110577004810324059 82
UVM_INFO @ 57111846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 4464030755662262207210184910669687328322013382192281504653393521559762844698 85
UVM_INFO @ 6289203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 85760253815873932362210850499507135874936775217915028808798990037653497971165 75
UVM_INFO @ 5653115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 71563620718974884037445885346999009751945470778607552907281086679214440167672 82
UVM_INFO @ 9159092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 22976712198852009466197871700859018674370005335231360959588546697803829771660 75
UVM_INFO @ 2939194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 108441158114917237945643854331354597357464674882821367402516424373631226027412 75
UVM_INFO @ 34004179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 23119936665444273032477782410849269966303075843094817127661603076237978909209 82
UVM_INFO @ 7941858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 66615340550831069731947135130136224262649220728413622180607964581634199273882 75
UVM_INFO @ 7644120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 107256220460353978076014671927849326576969410289136525984117960436170225870964 75
UVM_INFO @ 39652909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 20596599654956710564375808564382806121545168640464046053114158434821815290002 75
UVM_INFO @ 4139740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 6302871645600306359532578566612280638623072673586294053804071627884056075090 82
UVM_INFO @ 37870763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 39424629607515962267238244952056773451743251265834830281680119684287710928222 75
UVM_INFO @ 2838961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 64603465209582770527127963272565009049223107417062867040474833140775070323530 76
UVM_INFO @ 6002719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 86049949572686799280663400456083932187228205806325266988981504595650419762125 76
UVM_INFO @ 4549987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 6196283602967795880309438809599806494498672384170468029439903018199223076144 75
UVM_INFO @ 6107138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 98208108865971962785835379541326129522524627895619279085115427510075520983231 89
UVM_INFO @ 39210101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 38074263346535684275727149709288896751045310443534678727450384086846644681327 75
UVM_INFO @ 4764101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 68076696709305944618062015371206014773330849769933772918657032964511510704253 76
UVM_INFO @ 7025696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 40556216999272240699072360500732918094011654563434008438535415781199831735892 75
UVM_INFO @ 3768552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 107658789394215480946323582857106200162315692338968354164639909071330155456577 85
UVM_INFO @ 10683154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 11152142906900327414022953733967853663291550784841238745540424658804850970592 76
UVM_INFO @ 8284494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 57105140786015964820318091013780382591240248443490957324369766605027154973466 76
UVM_INFO @ 45272349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 68503565669326098732783180286883268899583260515774573773556886669953979468897 82
UVM_INFO @ 4111506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 102137802330128836486341873123229474925289104732872094447814983193281662916531 75
UVM_INFO @ 2285641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 80938976496593891537193418194912699945796482035859320155220222494971671763412 87
UVM_INFO @ 7033691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 114444443055439367763268208895753153895037767782969046679873150169763581401516 76
UVM_INFO @ 14052277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 272990825652684557411803094676026898913350824386495302385745291385205121773 75
UVM_INFO @ 2823278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 38696599742615781596835672955260137287670834400994412790271523459492626858511 75
UVM_INFO @ 4033460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 28457792154697321084569326126659327084073390573648141577103955294895159188124 75
UVM_INFO @ 37607856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 45155550241447916566658046291704537982436018634643975587400251181417632085478 78
UVM_INFO @ 3930041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 30 test runs
clkmgr_shadow_reg_errors_with_csr_rw 29810771931290019658576250111170731142404417087508002962381839683028633503891 75
UVM_INFO @ 2309880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 39451067879579837035076719576965374643715086879157954194836582388143814932603 75
UVM_INFO @ 4141062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 89919980843885478063742175388729159106815879145248392630356878772359678691266 75
UVM_INFO @ 78379283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 17168567062545407955318598920068385335704749605907266177725097044501904096322 76
UVM_INFO @ 13538593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 6541523189698387952625378218650259452010236434156903482446022088867684866495 75
UVM_INFO @ 31768923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 35665847619472658559310145939624490742847849652202919809934114773059274574590 75
UVM_INFO @ 5651008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 32470253998097581275310831842457832704929517450120940711966804168632046959745 93
UVM_INFO @ 35296851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 111144882785948151675174745011215657577279774862814208827907817301771781222539 75
UVM_INFO @ 12542567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 13162895074143836141839626458965380819722446019860761311724431138188569464893 75
UVM_INFO @ 4522500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 100713493693071767599264475608135485595642201252394425582227880818560889929377 76
UVM_INFO @ 15424411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 34569615445586338358434875215874118604724694786284924939704314095751009908767 78
UVM_INFO @ 8046563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 35949094635981070945066913554576331431470601866850835545861360953526568985473 75
UVM_INFO @ 2212566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 57848623121230895662832940307516284085941239314942593240364735283335297254449 75
UVM_INFO @ 3153463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 51714059623811511737481552026397970344447690987340269024402021853385121541431 76
UVM_INFO @ 30725513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 95040660498057537202394744922257685196993746767267081814723038321930809114183 85
UVM_INFO @ 4233220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 84197327108557084889445662314173948494805148561256643861306613843142275262109 75
UVM_INFO @ 6385218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 98671576416110799673692401341659844816100903043876342954540748763771814079416 86
UVM_INFO @ 7772742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 6696473421076108440808878737921514161473559210592650403419970256318072065014 75
UVM_INFO @ 3488047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 55307799583408669365717409579877598597249936052776423104340627567590275766653 85
UVM_INFO @ 3795787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 16969916098404965445919822684745779094222841273281451252143145175198625246566 76
UVM_INFO @ 8650693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 55339598998235752949026639787670299864666904143109061906769064377424766487304 78
UVM_INFO @ 7964258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 39734519360671827569743000282058209814785896980907524252244717864203646833407 75
UVM_INFO @ 3110695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 62133546561976488505134721537676815512974646804963706011583167085371871092849 75
UVM_INFO @ 8753476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 112141410074217448560620829145703743536429273813906279316858934773359747759902 82
UVM_INFO @ 5709493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 58091269016675446551476762477204329529654412858795215078222356969911448494862 75
UVM_INFO @ 4167816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 115611863942589398272302923232671289853261442292537139888060059456116280156586 75
UVM_INFO @ 3218285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 91417819908317230517801681706054341335644733865730131481982816558278445119253 76
UVM_INFO @ 20867817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 109884746189387044663694784882954882864068429945057034028498566869284601920292 75
UVM_INFO @ 11541278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 39409036306946233693327664647262849254134968336654574729136643562810806164311 75
UVM_INFO @ 19858796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 46005816856824832440781130514000366055211098368561209587379404937458760597691 76
UVM_INFO @ 42451453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 29 test runs
clkmgr_regwen 55915001927172488695077870645101914341679118403915031045302084714083345171075 74
UVM_INFO @ 10932883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 38081979549398343121937522041132662455566671171446337768160766671921300546265 74
UVM_INFO @ 1771532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 15286422875114977820673806134925703702365663516676138680459729837975486926799 74
UVM_INFO @ 5194520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 56972556901837198166464148982115328934366511386114625182559885935057536602632 74
UVM_INFO @ 2961709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 106163134603000079164656445414815860312940418276713257942800168211267998928108 74
UVM_INFO @ 4951460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 8044839681350237983064873326938216529883310598206747358606667320969416033371 74
UVM_INFO @ 2789403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 9661373038644220772721096982766343616935838228111471817441078830683440830175 74
UVM_INFO @ 4437681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 76533931618043702064502050243678729953654033130326927840553534277178222932740 74
UVM_INFO @ 2495247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 110358824989540514818320129806622038402898658722828075329713042764922233576831 74
UVM_INFO @ 5326601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 88530445165716643535902189753183449255933439077941855366907370210378369207796 74
UVM_INFO @ 5437375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 18153710069802013103601963557481074185793246603136708041855817716149244479818 74
UVM_INFO @ 5800789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 16102809598958128058897310822719702654481432959336505655228904315819524732831 74
UVM_INFO @ 3313157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 43109446069334564550513152635007698114530070660145613916296859126107602616013 74
UVM_INFO @ 7753201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 93758829860806672098662646853237538200671785354217500221641041678165087226707 74
UVM_INFO @ 8550521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 13470815606035010522227170565824408130872547482280972739586817961804668875253 74
UVM_INFO @ 2939602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 47214732103952128984687026649898539573635015547715783117498507158197775689915 74
UVM_INFO @ 5607902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 95626675558799648958482377886083909515923307658043055910302399933914002556034 74
UVM_INFO @ 6380628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 17240225311710226307698691158155471101954042740894293597058906935991259048537 74
UVM_INFO @ 19701821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 69559206788884330394378038470291027945886424870013305845913578166471909398818 74
UVM_INFO @ 6772751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 43556585404890916975914851136012375131453931949623357250985496214674863979780 74
UVM_INFO @ 16693831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 73604859298064874380765860433226876040808584015582146479506524548562248704834 74
UVM_INFO @ 10141286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 112625437408942345243146890080807081931378739002438691601867913703036687705431 74
UVM_INFO @ 7535439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 95293082025484114904839453676091545982734293819453099484418411552184606774469 74
UVM_INFO @ 1495909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 108535027805630692209240887102935585727258555402410896548758116059925653893861 74
UVM_INFO @ 7019159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 56597553230917102640064165972333389227724387422803924546972257290821976311234 74
UVM_INFO @ 6812467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 15222981324911832177965310310221294064355443383428436701329362363964407668414 74
UVM_INFO @ 2821394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 20797289781248482205038087687597287754732171888624091866881605993778425043354 74
UVM_INFO @ 5552241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 113782492778511195945173035958703243711176344698031601009132484016002909773675 74
UVM_INFO @ 6534715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 23128779448822370189406329503681334136451297547076144422988998821293658309269 74
UVM_INFO @ 4870121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 18 test runs
clkmgr_same_csr_outstanding 77714381163071784190503828437075993109748043087291489631234362472073551032558 75
UVM_INFO @ 17269003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_same_csr_outstanding 4781955211042874491863141591617361035469538093601668308461913191434749079299 75
UVM_INFO @ 2421511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_same_csr_outstanding 80046833493090923006380634422603700118197830620519669010673097159906275422717 75
UVM_INFO @ 15954501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_same_csr_outstanding 96284034518817512477070916876427658753654891965528291695713952340185965450716 75
UVM_INFO @ 85871217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_same_csr_outstanding 27764849295348875483240637061751932337869674889267051002572607466841525527860 75
UVM_INFO @ 13330772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_same_csr_outstanding 23070813749085241125765365297418192468769902538307234239903188609683380675803 75
UVM_INFO @ 10428424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_same_csr_outstanding 3723654288211555303543674940179168841040308302459546733365013542353080365154 75
UVM_INFO @ 52216803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_same_csr_outstanding 53607195477123413133682322971585727454742775413812169984907121217589768221834 75
UVM_INFO @ 3447095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_same_csr_outstanding 105330092812728293152249958897451778577009619549011858860345920676262841500541 75
UVM_INFO @ 26714709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_same_csr_outstanding 50450324223760419041152857324280662958914394259394220833937052027874470042676 75
UVM_INFO @ 5799557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_same_csr_outstanding 64218139734032971969845183287997657199834664887133156331245482493689572412322 75
UVM_INFO @ 4598048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_same_csr_outstanding 69609485407957145548903483255640181492442566042214790058554079501964000772405 75
UVM_INFO @ 22322821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_same_csr_outstanding 16350517509166758460413709728991635283428502424186833509021405135298431525785 75
UVM_INFO @ 38434314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_same_csr_outstanding 7205345744355514339209175899882571086042590134752579606304267003450489278353 75
UVM_INFO @ 20976452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_same_csr_outstanding 106683796213098916438174338357672204951565470426737207661309537208241582004007 75
UVM_INFO @ 6885877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_same_csr_outstanding 7931979054626173463231150206365173903140020943451380746834287644736328268014 75
UVM_INFO @ 7654236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_same_csr_outstanding 17661354689616889564689622399403683902649811926041105663418759185110866171867 75
UVM_INFO @ 7708563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_same_csr_outstanding 12060946589237872544109710721461648419972354515720346614814763542143775506643 75
UVM_INFO @ 29045364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 14 test runs
clkmgr_regwen 67266203107587392412069944906296638994182439068918012058866851388710522971342 74
UVM_INFO @ 6553534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 76027408717821713924367863490909070218819506813631974633601878341630861938591 74
UVM_INFO @ 20863377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 110629719502277743796047301001234688590497645802266247768369754587185797434413 74
UVM_INFO @ 3512814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 74114455899206435238173609335036939492612063273439109611411180726752922226800 74
UVM_INFO @ 10437389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 110857000333332925879397142578617919110417904415682572610541829798073046863277 74
UVM_INFO @ 5967050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 105664180564972818109899422469432772982156560655661781387742626437820247663138 74
UVM_INFO @ 4734097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 34587060308514499104284225605800578581136950153067808324150723369474318571826 74
UVM_INFO @ 2994877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 28093299555479326832176086536215356990105374751901814546716889508681075740734 74
UVM_INFO @ 2257753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 80202426197220954417141449906564721892697639366086286775736015954337683916788 74
UVM_INFO @ 14974934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 85027214729305399418463426868604702054108287603802021899659460251227330687487 74
UVM_INFO @ 7138568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 108226543632842826229740245432265031388529152113136204993608209295865322930319 74
UVM_INFO @ 2074804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 34968398762383411226454308664242884124428347950345902093958260278993394016032 74
UVM_INFO @ 4655980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 36593945748752333343225474864496955605230524793475003321921135124262329359471 74
UVM_INFO @ 6850569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 113909472036222993899270183253262139465703083682243864691513286938860390095257 74
UVM_INFO @ 7628890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 5 test runs
clkmgr_sec_cm 29858735289075488481802999132466430615801553835875016797373579751634836855961 111
UVM_INFO @ 10134003189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 95683175311563667402815157840868621505979348423018331547553174473503922948505 133
UVM_INFO @ 10142588613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 65236565859306975625117609009780532433516539202759611391339506247370367072989 117
UVM_INFO @ 10134340535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 93616075967138073212907363747692540591256479312248835765636735221203655210609 143
UVM_INFO @ 10084374454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 45971544773625947441355835529074203636555001533432234803718760212671267229084 97
UVM_INFO @ 10035923658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 5 test runs
clkmgr_csr_bit_bash 29390361853781133733670770211923493038707081306993308757547660556405548818005 75
UVM_INFO @ 24476600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_bit_bash 73109338563554791829804275964110696306870019355637943310631591376215678003514 75
UVM_INFO @ 326338617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_bit_bash 24687094590844923662845836618204926675139442257866447341148980448169367827817 75
UVM_INFO @ 118676857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_bit_bash 108749726314728394507067004848444898270891685890491895551053248379751024741448 75
UVM_INFO @ 54479241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_bit_bash 19032840719962280467003151191192907900401715402404455710273523252003447307836 75
UVM_INFO @ 20096866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
clkmgr_shadow_reg_errors 93614111208052100052589391583774798690612402554503855270936034605775546918474 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 86844328101178479913952315042670570562812534643121927116323554762455249388385 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 78935168355994010039869103044283854525168851677649906748200779761166475236505 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 30012818403667114139178157219692907554482941295012669855947539926519726212714 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 89684482256890514618456440462253093970909567280127736683957883545738657909087 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en 4 test runs
clkmgr_regwen 62947429975730177542543692571598586118088419890558976351100959146657580922092 74
UVM_INFO @ 17098523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 60646622724487332032899232575097357618106619592813949714988221987912494901501 74
UVM_INFO @ 3770326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 90072605228925304754613316086351895629585169424788760241737169461674281824394 74
UVM_INFO @ 26151380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_regwen 10061400562459155223481258194959066586282738872606936184779113936158348238628 74
UVM_INFO @ 4367460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:253) scoreboard [scoreboard] alert recov_fault has unexpected signal int error 1 test run
clkmgr_regwen 14784361285077364384384242686218762788104752610474783929547435042881814886111 74
UVM_INFO @ 49695428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---