Simulation Results: csrng

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.78 %
  • code
  • 96.20 %
  • assert
  • 97.16 %
  • func
  • 90.97 %
  • block
  • 98.53 %
  • line
  • 99.54 %
  • branch
  • 96.38 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
99.05%
V2
96.73%
V2S
98.29%
V3
10.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
csrng_smoke 5.000s 320.875us 50 50 100.00
csr_hw_reset 5 5 100.00
csrng_csr_hw_reset 33.000s 17.053us 5 5 100.00
csr_rw 20 20 100.00
csrng_csr_rw 33.000s 26.400us 20 20 100.00
csr_bit_bash 5 5 100.00
csrng_csr_bit_bash 47.000s 308.288us 5 5 100.00
csr_aliasing 5 5 100.00
csrng_csr_aliasing 34.000s 89.977us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
csrng_csr_mem_rw_with_rand_reset 302.000s 10011.588us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
csrng_csr_rw 33.000s 26.400us 20 20 100.00
csrng_csr_aliasing 34.000s 89.977us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 35.000s 75.828us 200 200 100.00
alerts 500 500 100.00
csrng_alert 67.000s 4633.574us 500 500 100.00
err 500 500 100.00
csrng_err 33.000s 28.223us 500 500 100.00
cmds 4 50 8.00
csrng_cmds 278.000s 19374.783us 4 50 8.00
life cycle 4 50 8.00
csrng_cmds 278.000s 19374.783us 4 50 8.00
stress_all 48 50 96.00
csrng_stress_all 905.000s 56495.403us 48 50 96.00
intr_test 50 50 100.00
csrng_intr_test 33.000s 15.614us 50 50 100.00
alert_test 50 50 100.00
csrng_alert_test 34.000s 209.974us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
csrng_tl_errors 11.000s 630.904us 20 20 100.00
tl_d_illegal_access 20 20 100.00
csrng_tl_errors 11.000s 630.904us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
csrng_csr_hw_reset 33.000s 17.053us 5 5 100.00
csrng_csr_rw 33.000s 26.400us 20 20 100.00
csrng_csr_aliasing 34.000s 89.977us 5 5 100.00
csrng_same_csr_outstanding 28.000s 131.239us 20 20 100.00
tl_d_partial_access 50 50 100.00
csrng_csr_hw_reset 33.000s 17.053us 5 5 100.00
csrng_csr_rw 33.000s 26.400us 20 20 100.00
csrng_csr_aliasing 34.000s 89.977us 5 5 100.00
csrng_same_csr_outstanding 28.000s 131.239us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
csrng_sec_cm 28.000s 981.639us 5 5 100.00
csrng_tl_intg_err 46.000s 1815.791us 20 20 100.00
sec_cm_config_regwen 49 70 70.00
csrng_regwen 32.000s 26.802us 29 50 58.00
csrng_csr_rw 33.000s 26.400us 20 20 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 67.000s 4633.574us 500 500 100.00
sec_cm_intersig_mubi 48 50 96.00
csrng_stress_all 905.000s 56495.403us 48 50 96.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 35.000s 75.828us 200 200 100.00
csrng_err 33.000s 28.223us 500 500 100.00
csrng_sec_cm 28.000s 981.639us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 35.000s 75.828us 200 200 100.00
csrng_err 33.000s 28.223us 500 500 100.00
csrng_sec_cm 28.000s 981.639us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 35.000s 75.828us 200 200 100.00
csrng_err 33.000s 28.223us 500 500 100.00
csrng_sec_cm 28.000s 981.639us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 35.000s 75.828us 200 200 100.00
csrng_err 33.000s 28.223us 500 500 100.00
csrng_sec_cm 28.000s 981.639us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 35.000s 75.828us 200 200 100.00
csrng_err 33.000s 28.223us 500 500 100.00
csrng_sec_cm 28.000s 981.639us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 67.000s 4633.574us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 35.000s 75.828us 200 200 100.00
csrng_err 33.000s 28.223us 500 500 100.00
sec_cm_constants_lc_gated 48 50 96.00
csrng_stress_all 905.000s 56495.403us 48 50 96.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 67.000s 4633.574us 500 500 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
csrng_tl_intg_err 46.000s 1815.791us 20 20 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 35.000s 75.828us 200 200 100.00
csrng_err 33.000s 28.223us 500 500 100.00
csrng_sec_cm 28.000s 981.639us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 35.000s 75.828us 200 200 100.00
csrng_err 33.000s 28.223us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 35.000s 75.828us 200 200 100.00
csrng_err 33.000s 28.223us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 35.000s 75.828us 200 200 100.00
csrng_err 33.000s 28.223us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 35.000s 75.828us 200 200 100.00
csrng_err 33.000s 28.223us 500 500 100.00
csrng_sec_cm 28.000s 981.639us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 35.000s 75.828us 200 200 100.00
csrng_err 33.000s 28.223us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 10 10.00
csrng_stress_all_with_rand_reset 10801.000s 0.000us 1 10 10.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 38 test runs
csrng_cmds 64416947698244579763038997652217551736170882244703864463791999634518240537999 100
UVM_INFO @ 79698041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 63151964520289872190386716644322891509444104525502188890767983321457440976355 100
UVM_INFO @ 82837469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 3828974059045982172017974259122993084710110621280111255605837901306265958593 100
UVM_INFO @ 39367892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 24958579282156834815794778429699829478152068185219196011661355745534349000841 100
UVM_INFO @ 379127727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 57023100647342450709498443367805769176453492751003984375064888070890489168427 100
UVM_INFO @ 189782564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 72062496991378858874793126492089084466277076196193674736676661920272701766620 100
UVM_INFO @ 202013727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 6958915644915385166258693953882870955270272826663786488977126383696424964510 100
UVM_INFO @ 614128675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 65747806939314293941126878126453846489557855803180135631164061798450129756147 100
UVM_INFO @ 227277039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 9141487728087903729919859555655952823385090727845422953729452665788200114774 100
UVM_INFO @ 81696105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 86856355914570639784387929112365078673622368416042345790105389169827017588827 100
UVM_INFO @ 292523872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 88115968632986724849059035537094347175278005922203630485424916211264448983231 110
UVM_INFO @ 264151912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 97114377177940645786346700387048501860989789822654430872601723027649316290619 100
UVM_INFO @ 93365038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 69712662511688779513097252113302291518720828122541218945632035853537044315006 100
UVM_INFO @ 480180252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 8910326686951787553352564090326585532201733578429071223621997139019035082599 100
UVM_INFO @ 699884710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 102441922809434449093386508430983602251536440962853980027843535524723295592420 100
UVM_INFO @ 160827212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 52080529138171010608803859457490831826929823986275807847236402983086740779304 100
UVM_INFO @ 85300224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 83465180726818612085464142892066272368132231590886493218627068327632384780833 100
UVM_INFO @ 243835896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 49783212008796924522643895802481479490619642999454291878952284444644831966601 100
UVM_INFO @ 21148474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 30337010086155531732242557726730758087228078538828229149089643554797885655196 100
UVM_INFO @ 331695756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 75237637083169546268260418828446389591171664966500034733045397878069297348138 100
UVM_INFO @ 177287270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 98661032030638638762664281418535212215992874387448428686514257563433612965905 100
UVM_INFO @ 1763395313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 83309044136515229371405435103768036333939916419074472340176312281078653982647 100
UVM_INFO @ 44305781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 28764485652270630185584091913698808069346609410540047022298864561058024032813 100
UVM_INFO @ 76305048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 58960632294899989842003963047153205350082018741865651682045611447055345661822 100
UVM_INFO @ 396599656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 50088880977117728995053271440360023402931010593786849369908612374382325703858 100
UVM_INFO @ 184920272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 47169013973361621165498197409061308716482754437607432302981937587532003292056 100
UVM_INFO @ 106642528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 113253896598324184288919171322835881437730018982803552070399497518479898942114 100
UVM_INFO @ 387027701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 53016539042965466204023579079613800269929977215223946694345795282625156818601 100
UVM_INFO @ 75076665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 45595224216204556848835123347674119555694910344480388228547215282747005024279 120
UVM_INFO @ 377826435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 75260783307747503681839695142089318215565879802005023653363715705395375067906 100
UVM_INFO @ 211424541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 111866470713214728291308735077937762649681354522244141994470135652261342403286 100
UVM_INFO @ 14878865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 111754938620681089723935189592040312697719314255963734243015890526049072273256 100
UVM_INFO @ 48151808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 114645563755264216199947746019754945355825851521812418896011112054722487303927 110
UVM_INFO @ 171326043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 28229186696994969522188146932748364806576468486185818798622078223756872325998 100
UVM_INFO @ 113055017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 115295913301811085764047573065401463177594363959842052886428718491083675155835 100
UVM_INFO @ 23203293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 2545749578587137960626864007351888529158099082612511576766498647821180342740 100
UVM_INFO @ 435336755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 96128314386820135790222725195285976233998804338722344406760355984967437483145 100
UVM_INFO @ 54551343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 57628061968910160093557030444725725301035372168023837613349283132683033397335 100
UVM_INFO @ 12051067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 16 test runs
csrng_regwen 23359234783689158142294860790455503766152692034844961336542907555850951082988 99
UVM_INFO @ 6032334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 48004381532072129730901059634566639336915056293875756377286560743597490555417 99
UVM_INFO @ 6773847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 61362759373701591129274651341572989675345172002748956901864949759627819655275 99
UVM_INFO @ 1449206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 81674811967908151691115250157656496830266464510039342046010290175955075992224 99
UVM_INFO @ 4533671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 91722848131042203931362617825172502141126290418925065316871443507115297911139 99
UVM_INFO @ 2797354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 67067339363999815481288185395534450587918463384044648057603477635977232388147 99
UVM_INFO @ 6683010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 64567773577402926971964541668925146425048137084829306689721694902124761194581 99
UVM_INFO @ 1303759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 104296310806748563948432276738063584235437386958752290605610194751959359893934 99
UVM_INFO @ 13851706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 49598678732569212292237620795532994189857446982786902005275240273479697208158 99
UVM_INFO @ 4985758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 67334110893637694685487810546228965025843956416232049894228312786534125145378 99
UVM_INFO @ 2564498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 75792798537219603331620913556882217372546145381587847053307177294351058988042 99
UVM_INFO @ 9141090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 80251874931733116537619244790786823665307148988827632492121922674285432258426 99
UVM_INFO @ 2721720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 33495243891819618038095496104375305362070741196889128179972776802792987997346 99
UVM_INFO @ 1982580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 109472486206262738037013215137398691573156930571735035071001806428911606795087 99
UVM_INFO @ 2799113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 54330485229009683051438843197697646109431448817631098745848526184715493122435 99
UVM_INFO @ 1458872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 109829446246277311203457106718467477835354076476939507715165260855125764433465 99
UVM_INFO @ 3617060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 5 test runs
csrng_regwen 62758349641866918003515888894275892971384412643430450690968470102367086732383 99
UVM_INFO @ 10946411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 21536037656798224228387718466418968114952831088810142785261149730346709086539 99
UVM_INFO @ 12974646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 113630684019514695574390951712604991218805201328878022866604745764080227917084 99
UVM_INFO @ 3847674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 106676143453776792030146236101979235302649176835495260362467505713359254217681 99
UVM_INFO @ 34241681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 104665848541729489367440973051062147788055080951680971649610130175668241111558 99
UVM_INFO @ 11735106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 4 test runs
csrng_stress_all_with_rand_reset 108954338452750471093137090213013983038350202274809781876672957405865712581701 None
csrng_stress_all_with_rand_reset 20755120385950563547004674243258242333704172516917167264180807332421012042918 None
csrng_stress_all_with_rand_reset 104768053044115795030018380537200176385523646267005428668051920092373112109899 None
csrng_stress_all_with_rand_reset 30537038675309113404933422689958081163157896468028906892803528160865853118063 None
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 4 test runs
csrng_stress_all_with_rand_reset 83644597430456327519655793596277962076311652369920111312482680412840216092984 104
UVM_INFO @ 44930306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 14134131762292119135369506995417431394278897806198167406928479343888677610425 184
UVM_INFO @ 7522796833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 8757274983232992853389915502614039755280611575645352638027049987851424738028 105
UVM_INFO @ 52882741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 44795839336688620254807375726546922091557808153344568458246668001714877510780 110
UVM_INFO @ 9000134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly 3 test runs
csrng_cmds 36602192340542629148634871965677609878232160827860770707844155224860336330329 108
UVM_INFO @ 9123207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 8859234800058684798483515634598079911146100902250066081126870276877985221703 108
UVM_INFO @ 74383195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 98008545556743423730095426416598815409961905543152923265819270217351673289283 108
UVM_INFO @ 35091604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 3 test runs
csrng_stress_all_with_rand_reset 49920961775751591427687403854497330831115234826201050579310834343443039614064 254
UVM_INFO @ 12336081519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 98975724112608266927354038153491839583525990564238135676437371976342069040919 109
UVM_INFO @ 209916653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 105490443035896782868775685572768653513855175382049516217691542432213091772474 120
UVM_INFO @ 16138846383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: csrng_reg_block.genbits 2 test runs
csrng_cmds 111904949271958780563680787289373287564835448900138749413236548203539532614582 103
UVM_INFO @ 62384704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 79237381335063080427612530001768579692405743590092904861783059244021338487657 103
UVM_INFO @ 292972287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:640) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*]) 2 test runs
csrng_cmds 7085643315417235809641351743949529239194367475723837651218084694351908746243 109
UVM_INFO @ 13087678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 96626149577878437327980886285066960136462861638162836650204766150984907461462 109
UVM_INFO @ 193203533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:304) [scoreboard] Check failed cmd_sts[SW_APP] == item.d_data[*:*] (* [*] vs * [*]) 1 test run
csrng_cmds 90285693330862181125678816371160588907351293142798578657435127399493428351757 108
UVM_INFO @ 9821121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [csrng_common_vseq] wait timeout occurred! 1 test run
csrng_csr_mem_rw_with_rand_reset 36343562004560963945760721448148883783533664183418230908798698164000161087749 106
UVM_INFO @ 10011587893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---