Simulation Results: dma

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.00 %
  • code
  • 92.20 %
  • assert
  • 96.61 %
  • func
  • 75.20 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 9.000s 328.934us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 8.000s 307.311us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 9.000s 349.583us 50 50 100.00
csr_hw_reset 5 5 100.00
dma_csr_hw_reset 2.000s 37.440us 5 5 100.00
csr_rw 20 20 100.00
dma_csr_rw 2.000s 15.740us 20 20 100.00
csr_bit_bash 5 5 100.00
dma_csr_bit_bash 18.000s 2751.459us 5 5 100.00
csr_aliasing 5 5 100.00
dma_csr_aliasing 7.000s 304.630us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 45.847us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
dma_csr_rw 2.000s 15.740us 20 20 100.00
dma_csr_aliasing 7.000s 304.630us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 116.000s 37266.545us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 307.000s 118648.352us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 491.000s 146091.448us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 491.000s 146091.448us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 307.000s 118648.352us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 1203.000s 200547.196us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 491.000s 146091.448us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 19.000s 14087.728us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 252.000s 27130.770us 3 3 100.00
alert_test 50 50 100.00
dma_alert_test 2.000s 50.968us 50 50 100.00
intr_test 50 50 100.00
dma_intr_test 2.000s 11.716us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
dma_tl_errors 5.000s 180.820us 20 20 100.00
tl_d_illegal_access 20 20 100.00
dma_tl_errors 5.000s 180.820us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
dma_csr_hw_reset 2.000s 37.440us 5 5 100.00
dma_csr_rw 2.000s 15.740us 20 20 100.00
dma_csr_aliasing 7.000s 304.630us 5 5 100.00
dma_same_csr_outstanding 4.000s 134.761us 20 20 100.00
tl_d_partial_access 50 50 100.00
dma_csr_hw_reset 2.000s 37.440us 5 5 100.00
dma_csr_rw 2.000s 15.740us 20 20 100.00
dma_csr_aliasing 7.000s 304.630us 5 5 100.00
dma_same_csr_outstanding 4.000s 134.761us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 25.000s 371.118us 5 5 100.00
dma_generic_stress 1203.000s 200547.196us 5 5 100.00
dma_handshake_stress 491.000s 146091.448us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 12.000s 346.491us 15 15 100.00
tl_intg_err 25 25 100.00
dma_tl_intg_err 5.000s 863.619us 20 20 100.00
dma_sec_cm 2.000s 67.067us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 188.000s 21692.311us 25 25 100.00
dma_longer_transfer 7.000s 216.289us 5 5 100.00
dma_stress_all_with_rand_reset 3.000s 214.779us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 4590992285253980956984485986972337128990276028242270662870808323108457532578 93
UVM_INFO @ 214779017ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---