Simulation Results: edn/edn0

 
22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.30 %
  • code
  • 95.26 %
  • assert
  • 98.89 %
  • func
  • 58.74 %
  • block
  • 96.95 %
  • line
  • 98.68 %
  • branch
  • 93.23 %
  • toggle
  • 89.13 %
  • FSM
  • 100.00 %
Validation stages
V1
99.05%
V2
99.18%
V2S
100.00%
V3
82.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 2.000s 48.945us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 3.000s 192.178us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 2.000s 25.608us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 8.000s 570.540us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 3.000s 102.380us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
edn_csr_mem_rw_with_rand_reset 49.000s 10013.710us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 2.000s 25.608us 20 20 100.00
edn_csr_aliasing 3.000s 102.380us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 77.000s 8737.461us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 77.000s 8737.461us 300 300 100.00
genbits 300 300 100.00
edn_genbits 77.000s 8737.461us 300 300 100.00
interrupts 50 50 100.00
edn_intr 2.000s 38.216us 50 50 100.00
alerts 200 200 100.00
edn_alert 3.000s 59.699us 200 200 100.00
errs 100 100 100.00
edn_err 3.000s 45.389us 100 100 100.00
disable 92 100 92.00
edn_disable 2.000s 21.455us 50 50 100.00
edn_disable_auto_req_mode 9.000s 500.000us 42 50 84.00
stress_all 50 50 100.00
edn_stress_all 9.000s 357.702us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 2.000s 21.241us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 3.000s 55.230us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 5.000s 642.572us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 5.000s 642.572us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 3.000s 192.178us 5 5 100.00
edn_csr_rw 2.000s 25.608us 20 20 100.00
edn_csr_aliasing 3.000s 102.380us 5 5 100.00
edn_same_csr_outstanding 3.000s 24.470us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 3.000s 192.178us 5 5 100.00
edn_csr_rw 2.000s 25.608us 20 20 100.00
edn_csr_aliasing 3.000s 102.380us 5 5 100.00
edn_same_csr_outstanding 3.000s 24.470us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 15.000s 1702.121us 5 5 100.00
edn_tl_intg_err 5.000s 314.324us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 2.000s 27.215us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 3.000s 59.699us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 15.000s 1702.121us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 15.000s 1702.121us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 15.000s 1702.121us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 15.000s 1702.121us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 3.000s 59.699us 200 200 100.00
edn_sec_cm 15.000s 1702.121us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 3.000s 59.699us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 5.000s 314.324us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 41 50 82.00
edn_stress_all_with_rand_reset 132.000s 18628.548us 41 50 82.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 8 test runs
edn_stress_all_with_rand_reset 27444443142464392662661945467809928030292862066990353438185834132699416988771 248
UVM_INFO @ 1915367093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 41683364731579533911482438812377110349968431189850826931134100061812573580837 327
UVM_INFO @ 2358320112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 50613805465245847923499240351202574059596783099585946846812271330250970364378 304
UVM_INFO @ 4034050509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 55865568935580734048533748191587332692907307804980355095813221200972617943275 188
UVM_INFO @ 1767192962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 23194031601118196104437042356420444827193483474072954807417047566269403927772 236
UVM_INFO @ 1668834141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 81366254471245645902419279359655452868055765330337430815780040087983477988684 199
UVM_INFO @ 753666341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 30196167196886806009716472183011119412260011624832821701473014316707693798445 345
UVM_INFO @ 2714469911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 79802172280675431071855048011675639470703463815102219300134224858598007920057 154
UVM_INFO @ 290454077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
edn_disable_auto_req_mode 46049880691364711516215907095224332953863829691342252002341836989482367148396 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 105766861000180614235277609209431051804738573029775085511600492947372782816483 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 70949453276581596170755909653479864530207760602021253162920814517689188893710 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 54791743488872692481312165825679585700810794211539090719795206998513524824604 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 85226854296893526104633767708374812523859525430760512821740179624424820548615 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:431) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 3 test runs
edn_disable_auto_req_mode 84570934162532342000813578400059209894695944805189283309206883576187456906760 103
UVM_INFO @ 46379479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 85713077799354040944442724973304053253209771137088227761200684198227770685245 103
UVM_INFO @ 38505816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 16527700833818298292627101686146523661389374745216198792466432486220055509324 103
UVM_INFO @ 286439091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_csr_mem_rw_with_rand_reset 4829383380138647847557730193978903375502563319760159145481180598452538299777 111
UVM_INFO @ 10013709892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1200) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
edn_stress_all_with_rand_reset 86600101554468086436513281459621588982969748807239323241393748648431200954346 208
UVM_INFO @ 751212277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---