Simulation Results

Simulation Results: edn/edn1

22/05/2026 15:00:33 DVSim: v1.49.0 sha: aa614ec json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.84 %

code
96.18 %

assert
98.70 %

func
92.65 %

line
98.48 %

branch
94.59 %

cond
95.08 %

toggle
96.15 %

FSM
96.59 %

Validation stages

V1		100.00%
V2		99.69%
V2S		100.00%
V3		88.00%

105/105 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	edn_smoke	1.200s	160.434us	50	50	100.00
csr_hw_reset				5	5	100.00
	edn_csr_hw_reset	1.480s	16.808us	5	5	100.00
csr_rw				20	20	100.00
	edn_csr_rw	1.340s	24.512us	20	20	100.00
csr_bit_bash				5	5	100.00
	edn_csr_bit_bash	4.850s	496.512us	5	5	100.00
csr_aliasing				5	5	100.00
	edn_csr_aliasing	1.530s	84.679us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	edn_csr_mem_rw_with_rand_reset	1.870s	33.670us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	edn_csr_rw	1.340s	24.512us	20	20	100.00
	edn_csr_aliasing	1.530s	84.679us	5	5	100.00

967/970 passed

99.69 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
firmware				300	300	100.00
	edn_genbits	126.440s	13654.653us	300	300	100.00
csrng_commands				300	300	100.00
	edn_genbits	126.440s	13654.653us	300	300	100.00
genbits				300	300	100.00
	edn_genbits	126.440s	13654.653us	300	300	100.00
interrupts				50	50	100.00
	edn_intr	1.530s	23.085us	50	50	100.00
alerts				200	200	100.00
	edn_alert	1.710s	32.595us	200	200	100.00
errs				100	100	100.00
	edn_err	1.480s	47.885us	100	100	100.00
disable				97	100	97.00
	edn_disable	1.370s	22.682us	50	50	100.00
	edn_disable_auto_req_mode	5.690s	500.000us	47	50	94.00
stress_all				50	50	100.00
	edn_stress_all	7.950s	395.153us	50	50	100.00
intr_test				50	50	100.00
	edn_intr_test	1.220s	58.361us	50	50	100.00
alert_test				50	50	100.00
	edn_alert_test	1.380s	16.802us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	edn_tl_errors	3.730s	125.078us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	edn_tl_errors	3.730s	125.078us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	edn_csr_hw_reset	1.480s	16.808us	5	5	100.00
	edn_csr_rw	1.340s	24.512us	20	20	100.00
	edn_csr_aliasing	1.530s	84.679us	5	5	100.00
	edn_same_csr_outstanding	1.420s	25.302us	20	20	100.00
tl_d_partial_access				50	50	100.00
	edn_csr_hw_reset	1.480s	16.808us	5	5	100.00
	edn_csr_rw	1.340s	24.512us	20	20	100.00
	edn_csr_aliasing	1.530s	84.679us	5	5	100.00
	edn_same_csr_outstanding	1.420s	25.302us	20	20	100.00

V2S

235/235 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	edn_sec_cm	4.330s	342.990us	5	5	100.00
	edn_tl_intg_err	11.170s	1059.369us	20	20	100.00
sec_cm_config_regwen				10	10	100.00
	edn_regwen	1.340s	82.494us	10	10	100.00
sec_cm_config_mubi				200	200	100.00
	edn_alert	1.710s	32.595us	200	200	100.00
sec_cm_main_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	4.330s	342.990us	5	5	100.00
sec_cm_ack_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	4.330s	342.990us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	edn_sec_cm	4.330s	342.990us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	edn_sec_cm	4.330s	342.990us	5	5	100.00
sec_cm_main_sm_ctr_local_esc				205	205	100.00
	edn_alert	1.710s	32.595us	200	200	100.00
	edn_sec_cm	4.330s	342.990us	5	5	100.00
sec_cm_cs_rdata_bus_consistency				200	200	100.00
	edn_alert	1.710s	32.595us	200	200	100.00
sec_cm_tile_link_bus_integrity				20	20	100.00
	edn_tl_intg_err	11.170s	1059.369us	20	20	100.00

44/50 passed

88.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				44	50	88.00
	edn_stress_all_with_rand_reset	113.540s	31893.964us	44	50	88.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				6 test runs
	edn_stress_all_with_rand_reset	36375744553631377828365192970609154621681053253504330517331785163473080448136	262	UVM_INFO @ 2368934437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	81234226955269190762577598462825110312565010391395372066451617070059289395449	333	UVM_INFO @ 5123769763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	53195057901518488224826936115348757637268107433491058807465745585487359477155	160	UVM_INFO @ 737501839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	38467768561814732340071905147500425274600692760505526866797722478296470461618	303	UVM_INFO @ 4138232910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	31982519786880106772264608755852455514155133506912135866518865662570069711008	238	UVM_INFO @ 1880066329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	62470345313644151200514466723655974982718638926770441507911204310156214162227	124	UVM_INFO @ 400672150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				3 test runs
	edn_disable_auto_req_mode	47682488181810337869128878805777411957335319597913034039547212937927509280459	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	98513598350995332595641611310632763172071611749567718241779666030859602854595	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	59979928878176149624688561729356701636805941616092874344939671503155420920387	89	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---